diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 20:23:53 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 13:02:27 +0300 |
| commit | 34856c5029683890435d48b44d11bf254fec2895 (patch) | |
| tree | db28ec29a94df31d5e2ed7e79cbe7de1ae3d7ee4 /drivers/pinctrl/renesas | |
| parent | efd5ee63e9d090ac5dca57abb3ef6d518c496a7d (diff) | |
| download | linux-34856c5029683890435d48b44d11bf254fec2895.tar.xz | |
pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
This reduces kernel size by 496 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/pinctrl/renesas')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a7796.c | 137 |
1 files changed, 32 insertions, 105 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index ece673f0af5d..a0096ef5e68d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -5094,23 +5094,11 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_16 RESERVED */ GP_0_15_FN, GPSR0_15, GP_0_14_FN, GPSR0_14, GP_0_13_FN, GPSR0_13, @@ -5162,24 +5150,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP2_31_15 RESERVED */ GP_2_14_FN, GPSR2_14, GP_2_13_FN, GPSR2_13, GP_2_12_FN, GPSR2_12, @@ -5196,23 +5171,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_16 RESERVED */ GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, GP_3_13_FN, GPSR3_13, @@ -5230,21 +5193,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_18 RESERVED */ GP_4_17_FN, GPSR4_17, GP_4_16_FN, GPSR4_16, GP_4_15_FN, GPSR4_15, @@ -5332,35 +5285,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, GPSR6_1, GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, + GROUP(-28, 1, 1, 1, 1), + GROUP( + /* GP7_31_4 RESERVED */ GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, @@ -5441,12 +5369,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_7_4 IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( + { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, + GROUP(4, 4, 4, 4, -4, 4, 4, 4), + GROUP( IP7_31_28 IP7_27_24 IP7_23_20 IP7_19_16 - /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_15_12 RESERVED */ IP7_11_8 IP7_7_4 IP7_3_0 )) @@ -5551,13 +5481,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_7_4 IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( - /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, + GROUP(-24, 4, 4), + GROUP( + /* IP18_31_8 RESERVED */ IP18_7_4 IP18_3_0 )) }, |