diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-11-13 16:35:20 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-20 12:58:46 +0300 |
| commit | 03fc60cd8e7b7e6f330d0a48c54545740addd9d8 (patch) | |
| tree | 627b522fc75419680ba867899d0b24d184a908c2 /drivers/pinctrl/renesas/pinctrl-rzg2l.c | |
| parent | 40384c840ea1944d7c5a392e8975ed088ecf0b37 (diff) | |
| download | linux-03fc60cd8e7b7e6f330d0a48c54545740addd9d8.tar.xz | |
pinctrl: renesas: rzg2l: Add audio clock pins on RZ/G3S
Add audio clock pins on the RZ/G3S SoC. These are used by audio IPs as
input pins to feed them with audio clocks.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241113133540.2005850-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/renesas/pinctrl-rzg2l.c')
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 1df9cec2873f..1a7be7d7b520 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2085,6 +2085,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | PIN_CFG_SOFT_PS)) }, { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | |