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author | Ninad Naik <quic_ninanaik@quicinc.com> | 2023-08-09 13:06:34 +0300 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2023-08-10 11:48:15 +0300 |
commit | 9757300d2750ef76f139aa6f5f7eadd61a0de0d3 (patch) | |
tree | 2d749b31308013606bcce7d5ac9314b3aae91cba /drivers/pinctrl/qcom/pinctrl-sa8775p.c | |
parent | f00295e890bbc8780cd2076ee17bc7a08a53091c (diff) | |
download | linux-9757300d2750ef76f139aa6f5f7eadd61a0de0d3.tar.xz |
pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets
SA8775 and newer target have added support for an increased number of
interrupt targets. To implement this change, the intr_target field, which
is used to configure the interrupt target in the interrupt configuration
register is increased from 3 bits to 4 bits.
In accordance to these updates, a new intr_target_width member is
introduced in msm_pingroup structure. This member stores the value of
width of intr_target field in the interrupt configuration register. This
value is used to dynamically calculate and generate mask for setting the
intr_target field. By default, this mask is set to 3 bit wide, to ensure
backward compatibility with the older targets.
Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms")
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/qcom/pinctrl-sa8775p.c')
-rw-r--r-- | drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 8a5cd15512b9..8fdea25d8d67 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -46,6 +46,7 @@ .intr_enable_bit = 0, \ .intr_status_bit = 0, \ .intr_target_bit = 5, \ + .intr_target_width = 4, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ |