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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-20 00:19:33 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-20 00:19:33 +0300 |
commit | 3c2edc36a77420d8be05d656019dbc8c31535992 (patch) | |
tree | 70d8c9abb04c89e82c79c46efd2f7cb1bf836ef5 /drivers/pinctrl/qcom/pinctrl-msm.c | |
parent | 32b90daf5cafdda62b1ce62d0b7445fa9107babf (diff) | |
parent | cb0438e4436085d89706b5ccfce4d5da531253de (diff) | |
download | linux-3c2edc36a77420d8be05d656019dbc8c31535992.tar.xz |
Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.4 kernel cycle:
Core changes:
- Fix errors in example code in the documentation.
New drivers:
- Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
Ingenic driver.
- Support Cirrus Logic Madera CS47L92 and CS47L15.
- Support Allwinner Sunxi V3S.
- Support Aspeed 2600 BMC.
- Support Qualcomm SC7180.
- Support Marvell MVEBU CS115.
Driver improvements:
- Clean up a few drivers to use the devm_platform_ioremap_resource()
helper.
- Pass the irqchip when registering the gpio_chip in some pin
controllers that are also GPIO controllers.
- Support suspend/resume in the Tegra driver.
- Support pull-up on the Broadcom BCM2711.
- The Intel driver can now request locked pads.
- Fix the UFS reset pin in the Qualcomm SDM845 driver"
* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
pinctrl: bcm: remove redundant assignment to pointer log
pinctrl: iproc: Add 'get_direction' support
pinctrl: iproc-gpio: Handle interrupts for multiple instances
pinctrl: iproc-gpio: Fix incorrect pinconf configurations
pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
pinctrl: qcom: sdm845: Fix UFS_RESET pin
pinctrl: mvebu: add additional variant for standalone CP115
pinctrl: mvebu: Add CP110 missing pin functionality
dt-bindings: cp110: document the new CP115 pinctrl compatible
pinctrl: bcm2835: Pass irqchip when adding gpiochip
pinctrl: meson: meson: Add of_node_put() before return
pinctrl/gpio: Take MUX usage into account
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
pinctrl: amd: disable spurious-firing GPIO IRQs
pinctrl: rza2: Include the appropriate headers
pinctrl: rza2: Drop driver use of consumer flags
...
Diffstat (limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
-rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm.c | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index b8a1c43222f8..763da0be10d6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -618,8 +618,7 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc, } /* The number of GPIOs in the ACPI tables */ - len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, - 0); + len = ret = device_property_count_u16(pctrl->dev, "gpios"); if (ret < 0) return 0; @@ -996,12 +995,13 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) if (pctrl->soc->reserved_gpios) return true; - return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; + return device_property_count_u16(pctrl->dev, "gpios") > 0; } static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; + struct gpio_irq_chip *girq; int ret; unsigned ngpio = pctrl->soc->ngpios; @@ -1028,6 +1028,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + girq = &chip->irq; + girq->chip = &pctrl->irq_chip; + girq->parent_handler = msm_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->parents[0] = pctrl->irq; + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); @@ -1054,20 +1066,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) } } - ret = gpiochip_irqchip_add(chip, - &pctrl->irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - gpiochip_remove(&pctrl->chip); - return -ENOSYS; - } - - gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, - msm_gpio_irq_handler); - return 0; } @@ -1161,10 +1159,8 @@ int msm_pinctrl_probe(struct platform_device *pdev, msm_pinctrl_setup_pm_reset(pctrl); pctrl->irq = platform_get_irq(pdev, 0); - if (pctrl->irq < 0) { - dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); + if (pctrl->irq < 0) return pctrl->irq; - } pctrl->desc.owner = THIS_MODULE; pctrl->desc.pctlops = &msm_pinctrl_ops; |