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authorPritesh Raithatha <praithatha@nvidia.com>2013-01-08 11:32:36 +0400
committerLinus Walleij <linus.walleij@linaro.org>2013-01-18 19:13:52 +0400
commit348d1bf75c09f854630e9bd161dc2a88aebe2149 (patch)
treeb7f3fd0f286d8191584c8d2f0200a29121e1acf2 /drivers/pinctrl/pinctrl-tegra30.c
parentb2083062a3b4035e85349120b426ecef2b6d155f (diff)
downloadlinux-348d1bf75c09f854630e9bd161dc2a88aebe2149.tar.xz
pinctrl: tegra: add support for rcv-sel and drive type
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e. rcv-sel and drive type. rcv-sel: Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH drv_type: Ouptput drive type: 33-50 ohm driver: 0x1 66-100ohm driver: 0x0 Add support of these parameters to be configure from DTS file. Tegra20 and Tegra30 does not support this configuration and hence initialize their pinmux structure with reg = -1. Originally written by Pritesh Raithatha. Changes by ldewangan: - remove drvtype_width as it is always 2. - Better describe the change. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra30.c')
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 9ad87ea735d4..2300deba25bd 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -3384,7 +3384,9 @@ static const struct tegra_function tegra30_functions[] = {
.ioreset_reg = PINGROUP_REG_##ior(r), \
.ioreset_bank = 1, \
.ioreset_bit = 8, \
+ .rcv_sel_reg = -1, \
.drv_reg = -1, \
+ .drvtype_reg = -1, \
}
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
@@ -3401,6 +3403,7 @@ static const struct tegra_function tegra30_functions[] = {
.odrain_reg = -1, \
.lock_reg = -1, \
.ioreset_reg = -1, \
+ .rcv_sel_reg = -1, \
.drv_reg = ((r) - DRV_PINGROUP_REG_A), \
.drv_bank = 0, \
.hsm_bit = hsm_b, \
@@ -3414,6 +3417,7 @@ static const struct tegra_function tegra30_functions[] = {
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
+ .drvtype_reg = -1, \
}
static const struct tegra_pingroup tegra30_groups[] = {