diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2017-01-27 13:07:14 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-01-30 17:01:35 +0300 |
| commit | e57725eabf87c9c75bc73bd19ea00e887155e43f (patch) | |
| tree | 93e55ff43d92764fd78a4810d531050a5eb5259f /drivers/pinctrl/intel/pinctrl-intel.h | |
| parent | 74694269116bf04a97d89dfce7489fde7eb41ab1 (diff) | |
| download | linux-e57725eabf87c9c75bc73bd19ea00e887155e43f.tar.xz | |
pinctrl: intel: Add support for hardware debouncer
The next generation Intel GPIO hardware has two additional registers
PADCFG2 and PADCFG3. The latter is marked as reserved but the former
includes configuration for per-pad hardware debouncer.
This patch adds support for that in the Intel pinctrl core driver. Since
these are additional features on top of the current generation hardware,
we use revision number and feature flags to enable this if detected.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-intel.h')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index c22c44485c5d..1ff5abf309e3 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -58,6 +58,7 @@ struct intel_function { * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE, etc. * @npins: Number of pins in this community + * @features: Additional features supported by the hardware * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * @ngpps: Number of groups (hw groups) in this community (reserved for @@ -72,11 +73,15 @@ struct intel_community { unsigned pin_base; unsigned gpp_size; size_t npins; + unsigned features; void __iomem *regs; void __iomem *pad_regs; size_t ngpps; }; +/* Additional features supported by the hardware */ +#define PINCTRL_FEATURE_DEBOUNCE BIT(0) + #define PIN_GROUP(n, p, m) \ { \ .name = (n), \ |