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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-01-31 01:48:30 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-01-31 01:48:30 +0300 |
| commit | 76a250f9a5f983c07e0735fac8370a584c520770 (patch) | |
| tree | 6dd225958563ce4ea8e7670c6fcb6e5c9fd7460a /drivers/phy | |
| parent | f8cc87b6c1e333ce7adc9fb2cb698d93b16eabe3 (diff) | |
| parent | b3506c7ed216dd2db1f06c2845da45018e2c508d (diff) | |
| download | linux-76a250f9a5f983c07e0735fac8370a584c520770.tar.xz | |
Merge branch 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo:
"Nothing too interesting. Several patches to convert mdelay() to
usleep_range(), removal of unused pata_at32, and other low level
driver specific changes"
* 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
ata: pata_pdc2027x: Replace mdelay with msleep
ata: pata_it821x: Replace mdelay with usleep_range in it821x_firmware_command
ata: sata_mv: Replace mdelay with usleep_range in mv_reset_channel
ata: remove pata_at32
phy: brcm-sata: remove unused variable
phy: brcm-sata: fix semicolon.cocci warnings
ata: ahci_brcm: Recover from failures to identify devices
phy: brcm-sata: Implement calibrate callback
ahci: Add Intel Cannon Lake PCH-H PCI ID
ata_piix: constify pci_bits
libata:pata_atiixp: Don't use unconnected secondary port on SB600
ata: ahci_brcm: Avoid clobbering SATA_TOP_CTRL_BUS_CTRL
ahci: Allow setting a default LPM policy for mobile chipsets
ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI
ahci: Annotate PCI ids for mobile Intel chipsets as such
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/broadcom/phy-brcm-sata.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c b/drivers/phy/broadcom/phy-brcm-sata.c index 3f953db70288..8708ea3b4d6d 100644 --- a/drivers/phy/broadcom/phy-brcm-sata.c +++ b/drivers/phy/broadcom/phy-brcm-sata.c @@ -150,6 +150,9 @@ enum sata_phy_regs { TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff, TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84, TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff, + + RXPMD_REG_BANK = 0x1c0, + RXPMD_RX_FREQ_MON_CONTROL1 = 0x87, }; enum sata_phy_ctrl_regs { @@ -505,8 +508,36 @@ static int brcm_sata_phy_init(struct phy *phy) return rc; } +static void brcm_stb_sata_calibrate(struct brcm_sata_port *port) +{ + void __iomem *base = brcm_sata_pcb_base(port); + u32 tmp = BIT(8); + + brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1, + ~tmp, tmp); +} + +static int brcm_sata_phy_calibrate(struct phy *phy) +{ + struct brcm_sata_port *port = phy_get_drvdata(phy); + int rc = -EOPNOTSUPP; + + switch (port->phy_priv->version) { + case BRCM_SATA_PHY_STB_28NM: + case BRCM_SATA_PHY_STB_40NM: + brcm_stb_sata_calibrate(port); + rc = 0; + break; + default: + break; + } + + return rc; +} + static const struct phy_ops phy_ops = { .init = brcm_sata_phy_init, + .calibrate = brcm_sata_phy_calibrate, .owner = THIS_MODULE, }; |