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authorMarek Vasut <marex@denx.de>2022-04-13 17:07:10 +0300
committerVinod Koul <vkoul@kernel.org>2022-04-20 12:15:55 +0300
commitf7f9abc5eab9d10561d74b20b3e284649e07d82f (patch)
treeeca2af94d44afb4b7be947fe9c2adafa115793dd /drivers/phy/rockchip/phy-rockchip-pcie.c
parent1599069a62c6179fdde9f6e5b54d44531064a79c (diff)
downloadlinux-f7f9abc5eab9d10561d74b20b3e284649e07d82f.tar.xz
phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED
The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first two options are handled correctly by the driver, the last one is not, this patch implements support for the last option. The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC internal PLL and output to PCIE_RESREF external IO pin. The last IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock are sourced from SoC internal PLL and not output anywhere. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-arm-kernel@lists.infradead.org To: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/rockchip/phy-rockchip-pcie.c')
0 files changed, 0 insertions, 0 deletions