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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-11 22:53:23 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-11 22:53:23 +0300 |
commit | 55d728b2b05fb0377a9048af3460c375b54619e2 (patch) | |
tree | 209f69d330086147cd53299cfdcaf0c13ff66650 /drivers/perf | |
parent | d3ea693439833b5ed9b932512e9a90b9381035c9 (diff) | |
parent | dd4bc60765873445893037ae73a5f75398a8cd19 (diff) | |
download | linux-55d728b2b05fb0377a9048af3460c375b54619e2.tar.xz |
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"arm64 fixes that came in during the merge window.
There will probably be more to come, but it doesn't seem like it's
worth me sitting on these in the meantime.
- Fix SCS debug check to report max stack usage in bytes as advertised
- Fix typo: CONFIG_FTRACE_WITH_REGS => CONFIG_DYNAMIC_FTRACE_WITH_REGS
- Fix incorrect mask in HiSilicon L3C perf PMU driver
- Fix compat vDSO compilation under some toolchain configurations
- Fix false UBSAN warning from ACPI IORT parsing code
- Fix booting under bootloaders that ignore TEXT_OFFSET
- Annotate debug initcall function with '__init'"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: warn on incorrect placement of the kernel by the bootloader
arm64: acpi: fix UBSAN warning
arm64: vdso32: add CONFIG_THUMB2_COMPAT_VDSO
drivers/perf: hisi: Fix wrong value for all counters enable
arm64: ftrace: Change CONFIG_FTRACE_WITH_REGS to CONFIG_DYNAMIC_FTRACE_WITH_REGS
arm64: debug: mark a function as __init to save some memory
scs: Report SCS usage in bytes rather than number of entries
Diffstat (limited to 'drivers/perf')
-rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c index 8dd1278bec04..7719ae4e2c56 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -35,7 +35,7 @@ /* L3C has 8-counters */ #define L3C_NR_COUNTERS 0x8 -#define L3C_PERF_CTRL_EN 0x20000 +#define L3C_PERF_CTRL_EN 0x10000 #define L3C_EVTYPE_NONE 0xff /* |