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authorBjorn Helgaas <bhelgaas@google.com>2020-01-30 02:00:07 +0300
committerBjorn Helgaas <bhelgaas@google.com>2020-01-30 02:00:07 +0300
commitb647d2bd8064c6a5113e7b50e3adbbf6108d7e21 (patch)
tree1906400fafb86e881979f3f79588f242c394e93e /drivers/pci
parentc11dfed9caa2a01237fd4281fc3b44b1e6425d8b (diff)
parent21a92676e1fe292acb077b13106b08c22ed36b14 (diff)
downloadlinux-b647d2bd8064c6a5113e7b50e3adbbf6108d7e21.tar.xz
Merge branch 'remotes/lorenzo/pci/tegra'
- Fix checking of pm_runtime_get_sync() return value (David Engraf) - Fix AFI_PEX2_CTRL reg offset for Tegra30 (Marcel Ziswiler) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 PCI: tegra: Fix return value check of pm_runtime_get_sync()
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/controller/pci-tegra.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 673a1725ef38..ac93f5a0398e 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.num_ports = 2,
.ports = tegra20_pcie_ports,
.msi_base_shift = 0,
- .afi_pex2_ctrl = 0x128,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
.pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.num_ports = 3,
.ports = tegra30_pcie_ports,
.msi_base_shift = 8,
+ .afi_pex2_ctrl = 0x128,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2798,7 +2798,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
pm_runtime_enable(pcie->dev);
err = pm_runtime_get_sync(pcie->dev);
- if (err) {
+ if (err < 0) {
dev_err(dev, "fail to enable pcie controller: %d\n", err);
goto teardown_msi;
}