Merge tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc

i.MX SoC changes for 3.15 from Shawn Guo:
 - Support suspend from ocram (DDR IO floating) for imx6 platforms
 - Add cpuidle support for imx6sl
 - Sparse warning fixes for imx6sl and vf610 clock code
 - Remove PWM platform code
 - Support ptp and rmii clock from pad
 - Support WEIM CS GPR configuration
 - Random cleanups and defconfig updates

* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
  ARM: imx6: drop .text.head section annotation from headsmp.S
  ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
  ARM: imx6: rename pm-imx6q.c to pm-imx6.c
  ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
  ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
  ARM: imx6: call suspend_set_ops() from suspend routine
  ARM: imx6: build headsmp.o only on CONFIG_SMP
  ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
  ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
  ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
  bus: imx-weim: support CS GPR configuration
  ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
  ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
  ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
  ARM: imx: add speed grading check for i.mx6 soc
  ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
  ARM: imx6q: support ptp and rmii clock from pad
  ARM: imx6q: remove unneeded clk lookups
  ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ...

1 files changed, 2 insertions, 9 deletions

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 13478ecd4113..0e79665afd44 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -60,14 +60,6 @@
 #define PCIE_DEBUG_CTRL         0x1a60
 #define  PCIE_DEBUG_SOFT_RESET		BIT(20)
 
-/*
- * This product ID is registered by Marvell, and used when the Marvell
- * SoC is not the root complex, but an endpoint on the PCIe bus. It is
- * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
- * bridge.
- */
-#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
-
 /* PCI configuration space of a PCI-to-PCI bridge */
 struct mvebu_sw_pci_bridge {
 	u16 vendor;
@@ -388,7 +380,8 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
 
 	bridge->class = PCI_CLASS_BRIDGE_PCI;
 	bridge->vendor = PCI_VENDOR_ID_MARVELL;
-	bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+	bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
+	bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
 	bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
 	bridge->cache_line_size = 0x10;