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author | Gabriele Paoloni <gabriele.paoloni@huawei.com> | 2015-10-08 22:27:43 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-11-02 23:48:38 +0300 |
commit | c003ca99632e1783466f459033874a0e1e31457b (patch) | |
tree | aef7d063a1baa25ddf71c83c2f1e155f83e6ad69 /drivers/pci/host/pci-exynos.c | |
parent | fa3b7cbab548b15da438b0cc13aa515f7f291f4d (diff) | |
download | linux-c003ca99632e1783466f459033874a0e1e31457b.tar.xz |
PCI: designware: Use exact access size in dw_pcie_cfg_read()
dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size
requested, but dw_pcie_cfg_read() previously performed a 32-bit read and
masked out the bits requested.
Use the exact access size in dw_pcie_cfg_read(). For example, if we want
an 8-bit read, use readb() instead of using readl() and masking out the 8
bits we need. This makes it symmetric with dw_pcie_cfg_write().
[bhelgaas: split into separate patch, set *val = 0 in failure case]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host/pci-exynos.c')
0 files changed, 0 insertions, 0 deletions