diff options
| author | Gustavo Pimentel <gustavo.pimentel@synopsys.com> | 2018-03-06 14:54:55 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-03-06 17:31:16 +0300 |
| commit | 1f319cb0538a10339d1ca73ee124331d611b43bf (patch) | |
| tree | ccd78704d15da4482172c0df4ff3511fd8923802 /drivers/pci/dwc/pcie-designware-host.c | |
| parent | 3f43ccc4ea1b912ff24679576b4278fafbb190b3 (diff) | |
| download | linux-1f319cb0538a10339d1ca73ee124331d611b43bf.tar.xz | |
PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed
over 8 controller registers, therefore the maximum number of MSI IRQs
can be changed to 256. The number of controllers can be calculated based
on the number of vectors used by the specific SoC driver.
Update the dwc host bridge driver maximum number of supported MSI
IRQs.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Niklas Cassel <niklas.cassel@axis.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-designware-host.c')
| -rw-r--r-- | drivers/pci/dwc/pcie-designware-host.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 193a0fa7b709..550fdbb5c226 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -76,11 +76,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = { /* MSI int handler */ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { - u32 val; int i, pos, irq; + u32 val, num_ctrls; irqreturn_t ret = IRQ_NONE; - for (i = 0; i < MAX_MSI_CTRLS; i++) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, &val); if (!val) @@ -639,13 +641,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) void dw_pcie_setup_rc(struct pcie_port *pp) { - u32 val, ctrl; + u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); dw_pcie_setup(pci); + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) + for (ctrl = 0; ctrl < num_ctrls; ctrl++) dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4, &pp->irq_status[ctrl]); /* setup RC BARs */ |