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| author | Vidya Sagar <vidyas@nvidia.com> | 2020-03-03 21:10:52 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-03-31 11:13:17 +0300 |
| commit | c57247f940e8ea13a0ec33378304dc3cdc5da4a8 (patch) | |
| tree | 9154236b232368b7df5bc7c0e3e0f38d66d8a419 /drivers/pci/controller/dwc/pcie-designware-ep.c | |
| parent | 9f04d18b1edf1992e1dd606933839d725aec9b1f (diff) | |
| download | linux-c57247f940e8ea13a0ec33378304dc3cdc5da4a8.tar.xz | |
PCI: tegra: Add support for PCIe endpoint mode in Tegra194
Add support for the endpoint mode of Synopsys DesignWare core based
dual mode PCIe controllers present in Tegra194 SoC.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-ep.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-ep.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dfbb806c25bf..8e9f31144b69 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -18,6 +18,7 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) pci_epc_linkup(epc); } +EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) { @@ -25,6 +26,7 @@ void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) pci_epc_init_notify(epc); } +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, int flags) @@ -536,6 +538,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return 0; } +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); int dw_pcie_ep_init(struct dw_pcie_ep *ep) { @@ -630,3 +633,4 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return dw_pcie_ep_init_complete(ep); } +EXPORT_SYMBOL_GPL(dw_pcie_ep_init); |