diff options
| author | Michael Chan <mchan@broadcom.com> | 2007-03-25 07:57:11 +0400 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-03-26 05:48:08 +0400 |
| commit | d18edcb212d7dc864a59e6aa9b6b9826299e0210 (patch) | |
| tree | 341955faabd7db53af392f4bdbd856dcbe6f8d11 /drivers/net/tg3.h | |
| parent | 1c46ae05d96f77f349ae60c799acb6ac6ddf07a8 (diff) | |
| download | linux-d18edcb212d7dc864a59e6aa9b6b9826299e0210.tar.xz | |
[TG3]: Exit irq handler during chip reset.
On most tg3 chips, the memory enable bit in the PCI command register
gets cleared during chip reset and must be restored before accessing
PCI registers using memory cycles. The chip does not generate
interrupt during chip reset, but the irq handler can still be called
because of irq sharing or irqpoll. Reading a register in the irq
handler can cause a master abort in this scenario and may result in a
crash on some architectures.
Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit
without touching any registers. The checking of the flag is in the
"slow" path of the irq handler and will not affect normal performance.
The msi handler is not shared and therefore does not require checking
the flag.
Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 5df8f76cdfe7..d515ed23841b 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -2223,6 +2223,7 @@ struct tg3 { #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 +#define TG3_FLAG_CHIP_RESETTING 0x40000000 #define TG3_FLAG_INIT_COMPLETE 0x80000000 u32 tg3_flags2; #define TG3_FLG2_RESTART_TIMER 0x00000001 |