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authorHeiner Kallweit <hkallweit1@gmail.com>2021-08-24 09:23:20 +0300
committerDavid S. Miller <davem@davemloft.net>2021-08-24 12:50:26 +0300
commit18a9eae240cb24d4771fed746c70662c0926a9e8 (patch)
tree4b2d023bafdf7ba3ac337f9e2f5f2d7d2bcca5bf /drivers/net/ethernet/marvell/mv643xx_eth.c
parent7fb9b66dc9ce52b058b3f9f3016b4d39f692c3b9 (diff)
downloadlinux-18a9eae240cb24d4771fed746c70662c0926a9e8.tar.xz
r8169: enable ASPM L0s state
ASPM is disabled completely because we've seen different types of problems in the past. However it seems these problems occurred with L1 or L1 sub-states only. On all the chip versions I've seen the acceptable L0s exit latency is 512ns. This should be short enough not to cause problems. If the actual L0s exit latency of the PCIe link is bigger than 512ns then the PCI core will disable L0s anyway. So let's give it a try and disable L1 and L1 sub-states only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/mv643xx_eth.c')
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