diff options
| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-10-29 14:16:59 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-01 09:29:35 +0300 |
| commit | 7380f79c111cf90481869f83986c355b403faf59 (patch) | |
| tree | a909c57bbf4ee0eb49578c68bd39aa614e0b1d5f /drivers/mtd | |
| parent | 17ccd0e4872290b5b24302b7520feefde03e5669 (diff) | |
| download | linux-7380f79c111cf90481869f83986c355b403faf59.tar.xz | |
mtd: spi-nor: Don't overwrite errno from Reg Ops
Do not overwrite the error numbers received the Register Operations
methods.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index e801f390728c..ef28b21c2447 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1364,10 +1364,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) spi_nor_write_enable(nor); - if (spi_nor_erase_chip(nor)) { - ret = -EIO; + ret = spi_nor_erase_chip(nor); + if (ret) goto erase_err; - } /* * Scale the timeout linearly with the size of the flash, with @@ -1839,7 +1838,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) ret = spi_nor_read_sr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading status register\n"); - return -EINVAL; + return ret; } sr_cr[0] = ret; sr_cr[1] = CR_QUAD_EN_SPAN; @@ -1870,7 +1869,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) ret = spi_nor_read_cr(nor); if (ret < 0) { dev_err(dev, "error while reading configuration register\n"); - return -EINVAL; + return ret; } if (ret & CR_QUAD_EN_SPAN) @@ -1882,7 +1881,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) ret = spi_nor_read_sr(nor); if (ret < 0) { dev_err(dev, "error while reading status register\n"); - return -EINVAL; + return ret; } sr_cr[0] = ret; @@ -1932,7 +1931,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) ret = spi_nor_write_sr2(nor, sr2); if (ret) { dev_err(nor->dev, "error while writing status register 2\n"); - return -EINVAL; + return ret; } ret = spi_nor_wait_till_ready(nor); |