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author | White Ding <bpqw@micron.com> | 2014-07-23 20:10:45 +0400 |
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committer | Brian Norris <computersforpeace@gmail.com> | 2014-08-19 22:53:07 +0400 |
commit | 57d3a9a89a0645f3597561e214f8d6852a2c56b4 (patch) | |
tree | 301383669e65312665f6c01820884bdb10ba3ee0 /drivers/mtd/chips/cfi_cmdset_0002.c | |
parent | 6f3c0f163103fb225c77b73ca17fc4ecea308103 (diff) | |
download | linux-57d3a9a89a0645f3597561e214f8d6852a2c56b4.tar.xz |
mtd: nand: fix nand_lock/unlock() function
Do nand reset before write protect check.
If we want to check the WP# low or high through STATUS READ and check bit 7,
we must reset the device, other operation (eg.erase/program a locked block) can
also clear the bit 7 of status register.
As we know the status register can be refreshed, if we do some operation to trigger it,
for example if we do erase/program operation to one block that is locked, then READ STATUS,
the bit 7 of READ STATUS will be 0 indicate the device in write protect, then if we do
erase/program operation to another block that is unlocked, the bit 7 of READ STATUS will
be 1 indicate the device is not write protect.
Suppose we checked the bit 7 of READ STATUS is 0 then judge the WP# is low (write protect),
but in this case the WP# maybe high if we do erase/program operation to a locked block,
so we must reset the device if we want to check the WP# low or high through STATUS READ and
check bit 7.
Signed-off-by: White Ding <bpqw@micron.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd/chips/cfi_cmdset_0002.c')
0 files changed, 0 insertions, 0 deletions