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author | Brian Norris <briannorris@chromium.org> | 2022-10-26 22:42:07 +0300 |
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committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-11-07 15:33:38 +0300 |
commit | 836078449464e6af3b66ae6652dae79af176f21e (patch) | |
tree | 0b105ba9ae3eeb02e56a19133e1aa74f68d5008b /drivers/mmc/host/cqhci-crypto.h | |
parent | fb1dec44c6750bb414f47b929c8c175a1a127c31 (diff) | |
download | linux-836078449464e6af3b66ae6652dae79af176f21e.tar.xz |
mmc: sdhci-tegra: Fix SDHCI_RESET_ALL for CQHCI
[[ NOTE: this is completely untested by the author, but included solely
because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix
SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other
drivers using CQHCI might benefit from a similar change, if they
also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same
bug on at least MSM, Arasan, and Intel hardware. ]]
SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't
tracking that properly in software. When out of sync, we may trigger
various timeouts.
It's not typical to perform resets while CQE is enabled, but this may
occur in some suspend or error recovery scenarios.
Include this fix by way of the new sdhci_and_cqhci_reset() helper.
This patch depends on (and should not compile without) the patch
entitled "mmc: cqhci: Provide helper for resetting both SDHCI and
CQHCI".
Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC")
Signed-off-by: Brian Norris <briannorris@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20221026124150.v4.5.I418c9eaaf754880fcd2698113e8c3ef821a944d7@changeid
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/cqhci-crypto.h')
0 files changed, 0 insertions, 0 deletions