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authorAlexander Usyskin <alexander.usyskin@intel.com>2015-08-02 22:20:52 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-08-04 03:33:54 +0300
commit1fa55b4e0e161b3d16b52f5bab1b39b39607bc27 (patch)
treebe74705f98e7de456914050cbe13ac11cd4af7d3 /drivers/misc/mei/hw-me-regs.h
parentbb9f4d26dda7d2a875cadc0f7eedee3d65d3d1f5 (diff)
downloadlinux-1fa55b4e0e161b3d16b52f5bab1b39b39607bc27.tar.xz
mei: me: d0i3: enable d0i3 interrupts
D0i3 adds additional interrupt reason bit, therefore we add a variable intr_source to save the interrupt causes for further dispatching. The interrupt cause is saved in the irq quick handler to achieve unified behavior for both MSI enabled and shared interrupt platforms. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/misc/mei/hw-me-regs.h')
-rw-r--r--drivers/misc/mei/hw-me-regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 4c8f05ea3651..8793ccca12ad 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -166,6 +166,10 @@
/* Host D0I3 Interrupt Status */
#define H_D0I3C_IS 0x00000040
+/* H_CSR masks */
+#define H_CSR_IE_MASK (H_IE | H_D0I3C_IE)
+#define H_CSR_IS_MASK (H_IS | H_D0I3C_IS)
+
/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
access to ME_CBD */