diff options
| author | Ohad Sharabi <osharabi@habana.ai> | 2021-04-21 13:03:21 +0300 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2021-06-18 15:23:39 +0300 |
| commit | c592c270fe1f24668ba9c9991d762e850333e63d (patch) | |
| tree | 0d92731b0707b7bf4b5256822ed7364589cfd26a /drivers/misc/habanalabs/goya | |
| parent | 22a795b4af5a7bc66335166054805c1f103c3e4d (diff) | |
| download | linux-c592c270fe1f24668ba9c9991d762e850333e63d.tar.xz | |
habanalabs: expose ASIC specific PCI info to common code
LKD has interfaces in which it receives device address.
For instance the debugfs_read/write variants receives device address for
CFG/SRAM/DRAM for read/write and need to translate to the mapped PCI BAR
address.
In addition, the dynamic FW load protocol dictates that the address to
which the LKD will copy the image for the next FW component will be
received as a device address and can be placed either in SRAM or DRAM.
We need to distinguish those regions as the access methods to those
regions are different (in DRAM we possibly need to set the BAR base).
Looking forward this code will be used to remove duplicated code in the
debugfs_read/write that search the memory region for the input device
address.
Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/goya')
| -rw-r--r-- | drivers/misc/habanalabs/goya/goya.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index dc5659340220..c3a241227fe0 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -849,6 +849,35 @@ void goya_late_fini(struct hl_device *hdev) hdev->hl_chip_info->info = NULL; } +static void goya_set_pci_memory_regions(struct hl_device *hdev) +{ + struct pci_mem_region *region; + + /* CFG */ + region = &hdev->pci_mem_region[PCI_REGION_CFG]; + region->region_base = CFG_BASE; + region->region_size = CFG_SIZE; + region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR; + region->bar_id = SRAM_CFG_BAR_ID; + region->used = 1; + + /* SRAM */ + region = &hdev->pci_mem_region[PCI_REGION_SRAM]; + region->region_base = SRAM_BASE_ADDR; + region->region_size = SRAM_SIZE; + region->offset_in_bar = 0; + region->bar_id = SRAM_CFG_BAR_ID; + region->used = 1; + + /* DRAM */ + region = &hdev->pci_mem_region[PCI_REGION_DRAM]; + region->region_base = DRAM_PHYS_BASE; + region->region_size = hdev->asic_prop.dram_size; + region->offset_in_bar = 0; + region->bar_id = DDR_BAR_ID; + region->used = 1; +} + /* * goya_sw_init - Goya software initialization code * @@ -919,6 +948,8 @@ static int goya_sw_init(struct hl_device *hdev) hdev->supports_coresight = true; hdev->supports_soft_reset = true; + goya_set_pci_memory_regions(hdev); + return 0; free_cpu_accessible_dma_pool: |