diff options
| author | Prashant Laddha <prladdha@cisco.com> | 2015-05-22 08:27:34 +0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-06-09 23:44:42 +0300 |
| commit | 061ddda681fea4a06befe1fc8e34ef2e0d14f5dc (patch) | |
| tree | 0ba7f6cdccf47edc82af869a09783031c292ec7e /drivers/media/i2c/adv7842.c | |
| parent | 8cf6874e84ba64488975a07fda267486a77ac5a3 (diff) | |
| download | linux-061ddda681fea4a06befe1fc8e34ef2e0d14f5dc.tar.xz | |
[media] v4l2-dv-timings: add interlace support in detect cvt/gtf
Extend detect_cvt/gtf API to indicate the format type (interlaced
or progressive). In case of interlaced, the vertical front and back
porch and vsync values for both (odd,even) fields are considered to
derive image height. Populated vsync, vertical front, back porch
values in bt timing structure for even and odd fields and updated
the flags appropriately.
Also modified the functions calling the detect_cvt/gtf(). As of now
these functions are calling detect_cvt/gtf() with interlaced flag
set to false.
Cc: Martin Bugge <marbugge@cisco.com>
Cc: Mats Randgaard <matrandg@cisco.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Prashant Laddha <prladdha@cisco.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers/media/i2c/adv7842.c')
| -rw-r--r-- | drivers/media/i2c/adv7842.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index f14ea78a7c9c..4cf79b2422d4 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -1445,12 +1445,12 @@ static int stdi2dv_timings(struct v4l2_subdev *sd, if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), - timings)) + false, timings)) return 0; if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), - state->aspect_ratio, timings)) + false, state->aspect_ratio, timings)) return 0; v4l2_dbg(2, debug, sd, |