isdn: whitespace coding style cleanup

isdn source code uses a not-current coding style.

Update the coding style used on a per-line basis
so that git diff -w shows only elided blank lines
at EOF.

Done with emacs and some scripts and some typing.

Built x86 allyesconfig.
No detected change in objdump -d or size.

Signed-off-by: Joe Perches <joe@perches.com>

1 files changed, 324 insertions, 324 deletions

diff --git a/drivers/isdn/hisax/hfc4s8s_l1.c b/drivers/isdn/hisax/hfc4s8s_l1.c
index 384d5118e325..dea04de8e7ca 100644
--- a/drivers/isdn/hisax/hfc4s8s_l1.c
+++ b/drivers/isdn/hisax/hfc4s8s_l1.c
@@ -93,32 +93,32 @@ static struct pci_device_id hfc4s8s_ids[] = {
 	 .subdevice = 0x08b4,
 	 .driver_data =
 	 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
-					    "HFC-4S Evaluation Board"}),
-	 },
+				 "HFC-4S Evaluation Board"}),
+	},
 	{.vendor = PCI_VENDOR_ID_CCD,
 	 .device = PCI_DEVICE_ID_8S,
 	 .subvendor = 0x1397,
 	 .subdevice = 0x16b8,
 	 .driver_data =
 	 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
-					    "HFC-8S Evaluation Board"}),
-	 },
+				 "HFC-8S Evaluation Board"}),
+	},
 	{.vendor = PCI_VENDOR_ID_CCD,
 	 .device = PCI_DEVICE_ID_4S,
 	 .subvendor = 0x1397,
 	 .subdevice = 0xb520,
 	 .driver_data =
 	 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
-					    "IOB4ST"}),
-	 },
+				 "IOB4ST"}),
+	},
 	{.vendor = PCI_VENDOR_ID_CCD,
 	 .device = PCI_DEVICE_ID_8S,
 	 .subvendor = 0x1397,
 	 .subdevice = 0xb522,
 	 .driver_data =
 	 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
-					    "IOB8ST"}),
-	 },
+				 "IOB8ST"}),
+	},
 	{}
 };
 
@@ -203,14 +203,14 @@ typedef struct _hfc4s8s_hw {
 #ifdef HISAX_HFC4S8S_PCIMEM	/* inline functions memory mapped */
 
 /* memory write and dummy IO read to avoid PCI byte merge problems */
-#define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);}
+#define Write_hfc8(a, b, c) {(*((volatile u_char *)(a->membase + b)) = c); inb(a->iobase + 4);}
 /* memory write without dummy IO access for fifo data access */
-#define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c)
-#define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b)))
-#define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c)
-#define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b)))
-#define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c)
-#define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b)))
+#define fWrite_hfc8(a, b, c) (*((volatile u_char *)(a->membase + b)) = c)
+#define Read_hfc8(a, b) (*((volatile u_char *)(a->membase + b)))
+#define Write_hfc16(a, b, c) (*((volatile unsigned short *)(a->membase + b)) = c)
+#define Read_hfc16(a, b) (*((volatile unsigned short *)(a->membase + b)))
+#define Write_hfc32(a, b, c) (*((volatile unsigned long *)(a->membase + b)) = c)
+#define Read_hfc32(a, b) (*((volatile unsigned long *)(a->membase + b)))
 #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));}
 #define PCI_ENA_MEMIO	0x03
 
@@ -218,87 +218,87 @@ typedef struct _hfc4s8s_hw {
 
 /* inline functions io mapped */
 static inline void
-SetRegAddr(hfc4s8s_hw * a, u_char b)
+SetRegAddr(hfc4s8s_hw *a, u_char b)
 {
 	outb(b, (a->iobase) + 4);
 }
 
 static inline u_char
-GetRegAddr(hfc4s8s_hw * a)
+GetRegAddr(hfc4s8s_hw *a)
 {
 	return (inb((volatile u_int) (a->iobase + 4)));
 }
 
 
 static inline void
-Write_hfc8(hfc4s8s_hw * a, u_char b, u_char c)
+Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c)
 {
 	SetRegAddr(a, b);
 	outb(c, a->iobase);
 }
 
 static inline void
-fWrite_hfc8(hfc4s8s_hw * a, u_char c)
+fWrite_hfc8(hfc4s8s_hw *a, u_char c)
 {
 	outb(c, a->iobase);
 }
 
 static inline void
-Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c)
+Write_hfc16(hfc4s8s_hw *a, u_char b, u_short c)
 {
 	SetRegAddr(a, b);
 	outw(c, a->iobase);
 }
 
 static inline void
-Write_hfc32(hfc4s8s_hw * a, u_char b, u_long c)
+Write_hfc32(hfc4s8s_hw *a, u_char b, u_long c)
 {
 	SetRegAddr(a, b);
 	outl(c, a->iobase);
 }
 
 static inline void
-fWrite_hfc32(hfc4s8s_hw * a, u_long c)
+fWrite_hfc32(hfc4s8s_hw *a, u_long c)
 {
 	outl(c, a->iobase);
 }
 
 static inline u_char
-Read_hfc8(hfc4s8s_hw * a, u_char b)
+Read_hfc8(hfc4s8s_hw *a, u_char b)
 {
 	SetRegAddr(a, b);
 	return (inb((volatile u_int) a->iobase));
 }
 
 static inline u_char
-fRead_hfc8(hfc4s8s_hw * a)
+fRead_hfc8(hfc4s8s_hw *a)
 {
 	return (inb((volatile u_int) a->iobase));
 }
 
 
 static inline u_short
-Read_hfc16(hfc4s8s_hw * a, u_char b)
+Read_hfc16(hfc4s8s_hw *a, u_char b)
 {
 	SetRegAddr(a, b);
 	return (inw((volatile u_int) a->iobase));
 }
 
 static inline u_long
-Read_hfc32(hfc4s8s_hw * a, u_char b)
+Read_hfc32(hfc4s8s_hw *a, u_char b)
 {
 	SetRegAddr(a, b);
 	return (inl((volatile u_int) a->iobase));
 }
 
 static inline u_long
-fRead_hfc32(hfc4s8s_hw * a)
+fRead_hfc32(hfc4s8s_hw *a)
 {
 	return (inl((volatile u_int) a->iobase));
 }
 
 static inline void
-wait_busy(hfc4s8s_hw * a)
+wait_busy(hfc4s8s_hw *a)
 {
 	SetRegAddr(a, R_STATUS);
 	while (inb((volatile u_int) a->iobase) & M_BUSY);
@@ -313,7 +313,7 @@ wait_busy(hfc4s8s_hw * a)
 /* may be updated by the chip during read             */
 /******************************************************/
 static u_char
-Read_hfc8_stable(hfc4s8s_hw * hw, int reg)
+Read_hfc8_stable(hfc4s8s_hw *hw, int reg)
 {
 	u_char ref8;
 	u_char in8;
@@ -325,7 +325,7 @@ Read_hfc8_stable(hfc4s8s_hw * hw, int reg)
 }
 
 static int
-Read_hfc16_stable(hfc4s8s_hw * hw, int reg)
+Read_hfc16_stable(hfc4s8s_hw *hw, int reg)
 {
 	int ref16;
 	int in16;
@@ -349,67 +349,67 @@ dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
 
 	switch (pr) {
 
-		case (PH_DATA | REQUEST):
-			if (!l1->enabled) {
-				dev_kfree_skb(skb);
-				break;
-			}
-			spin_lock_irqsave(&l1->lock, flags);
-			skb_queue_tail(&l1->d_tx_queue, skb);
-			if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
-			    (l1->tx_cnt <= 0)) {
-				l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
-				    0x10;
-				spin_unlock_irqrestore(&l1->lock, flags);
-				schedule_work(&l1->hw->tqueue);
-			} else
-				spin_unlock_irqrestore(&l1->lock, flags);
+	case (PH_DATA | REQUEST):
+		if (!l1->enabled) {
+			dev_kfree_skb(skb);
 			break;
+		}
+		spin_lock_irqsave(&l1->lock, flags);
+		skb_queue_tail(&l1->d_tx_queue, skb);
+		if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
+		    (l1->tx_cnt <= 0)) {
+			l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
+				0x10;
+			spin_unlock_irqrestore(&l1->lock, flags);
+			schedule_work(&l1->hw->tqueue);
+		} else
+			spin_unlock_irqrestore(&l1->lock, flags);
+		break;
 
-		case (PH_ACTIVATE | REQUEST):
-			if (!l1->enabled)
-				break;
-			if (!l1->nt_mode) {
-				if (l1->l1_state < 6) {
-					spin_lock_irqsave(&l1->lock,
-							  flags);
-
-					Write_hfc8(l1->hw, R_ST_SEL,
-						   l1->st_num);
-					Write_hfc8(l1->hw, A_ST_WR_STA,
-						   0x60);
-					mod_timer(&l1->l1_timer,
-						  jiffies + L1_TIMER_T3);
-					spin_unlock_irqrestore(&l1->lock,
-							       flags);
-				} else if (l1->l1_state == 7)
-					l1->d_if.ifc.l1l2(&l1->d_if.ifc,
-							  PH_ACTIVATE |
-							  INDICATION,
-							  NULL);
-			} else {
-				if (l1->l1_state != 3) {
-					spin_lock_irqsave(&l1->lock,
-							  flags);
-					Write_hfc8(l1->hw, R_ST_SEL,
-						   l1->st_num);
-					Write_hfc8(l1->hw, A_ST_WR_STA,
-						   0x60);
-					spin_unlock_irqrestore(&l1->lock,
-							       flags);
-				} else if (l1->l1_state == 3)
-					l1->d_if.ifc.l1l2(&l1->d_if.ifc,
-							  PH_ACTIVATE |
-							  INDICATION,
-							  NULL);
-			}
+	case (PH_ACTIVATE | REQUEST):
+		if (!l1->enabled)
 			break;
+		if (!l1->nt_mode) {
+			if (l1->l1_state < 6) {
+				spin_lock_irqsave(&l1->lock,
+						  flags);
+
+				Write_hfc8(l1->hw, R_ST_SEL,
+					   l1->st_num);
+				Write_hfc8(l1->hw, A_ST_WR_STA,
+					   0x60);
+				mod_timer(&l1->l1_timer,
+					  jiffies + L1_TIMER_T3);
+				spin_unlock_irqrestore(&l1->lock,
+						       flags);
+			} else if (l1->l1_state == 7)
+				l1->d_if.ifc.l1l2(&l1->d_if.ifc,
+						  PH_ACTIVATE |
+						  INDICATION,
+						  NULL);
+		} else {
+			if (l1->l1_state != 3) {
+				spin_lock_irqsave(&l1->lock,
+						  flags);
+				Write_hfc8(l1->hw, R_ST_SEL,
+					   l1->st_num);
+				Write_hfc8(l1->hw, A_ST_WR_STA,
+					   0x60);
+				spin_unlock_irqrestore(&l1->lock,
+						       flags);
+			} else if (l1->l1_state == 3)
+				l1->d_if.ifc.l1l2(&l1->d_if.ifc,
+						  PH_ACTIVATE |
+						  INDICATION,
+						  NULL);
+		}
+		break;
 
-		default:
-			printk(KERN_INFO
-			       "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
-			       pr);
-			break;
+	default:
+		printk(KERN_INFO
+		       "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
+		       pr);
+		break;
 	}
 	if (!l1->enabled)
 		l1->d_if.ifc.l1l2(&l1->d_if.ifc,
@@ -430,199 +430,199 @@ bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
 
 	switch (pr) {
 
-		case (PH_DATA | REQUEST):
-			if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
-				dev_kfree_skb(skb);
-				break;
-			}
-			spin_lock_irqsave(&l1->lock, flags);
-			skb_queue_tail(&bch->tx_queue, skb);
-			if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
-				l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
-				    ((bch->bchan == 1) ? 1 : 4);
-				spin_unlock_irqrestore(&l1->lock, flags);
-				schedule_work(&l1->hw->tqueue);
-			} else
-				spin_unlock_irqrestore(&l1->lock, flags);
+	case (PH_DATA | REQUEST):
+		if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
+			dev_kfree_skb(skb);
 			break;
+		}
+		spin_lock_irqsave(&l1->lock, flags);
+		skb_queue_tail(&bch->tx_queue, skb);
+		if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
+			l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
+				((bch->bchan == 1) ? 1 : 4);
+			spin_unlock_irqrestore(&l1->lock, flags);
+			schedule_work(&l1->hw->tqueue);
+		} else
+			spin_unlock_irqrestore(&l1->lock, flags);
+		break;
 
-		case (PH_ACTIVATE | REQUEST):
-		case (PH_DEACTIVATE | REQUEST):
-			if (!l1->enabled)
-				break;
-			if (pr == (PH_DEACTIVATE | REQUEST))
-				mode = L1_MODE_NULL;
-
-			switch (mode) {
-				case L1_MODE_HDLC:
-					spin_lock_irqsave(&l1->lock,
-							  flags);
-					l1->hw->mr.timer_usg_cnt++;
-					l1->hw->mr.
-					    fifo_slow_timer_service[l1->
-								    st_num]
-					    |=
-					    ((bch->bchan ==
-					      1) ? 0x2 : 0x8);
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 0 : 2)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_CON_HDLC, 0xc);	/* HDLC mode, flag fill, connect ST */
-					Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
-					Write_hfc8(l1->hw, A_IRQ_MSK, 1);	/* enable TX interrupts for hdlc */
-					Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
-					wait_busy(l1->hw);
-
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 1 : 3)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_CON_HDLC, 0xc);	/* HDLC mode, flag fill, connect ST */
-					Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
-					Write_hfc8(l1->hw, A_IRQ_MSK, 1);	/* enable RX interrupts for hdlc */
-					Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
-
-					Write_hfc8(l1->hw, R_ST_SEL,
-						   l1->st_num);
-					l1->hw->mr.r_ctrl0 |=
-					    (bch->bchan & 3);
-					Write_hfc8(l1->hw, A_ST_CTRL0,
-						   l1->hw->mr.r_ctrl0);
-					bch->mode = L1_MODE_HDLC;
-					spin_unlock_irqrestore(&l1->lock,
-							       flags);
-
-					bch->b_if.ifc.l1l2(&bch->b_if.ifc,
-							   PH_ACTIVATE |
-							   INDICATION,
-							   NULL);
-					break;
-
-				case L1_MODE_TRANS:
-					spin_lock_irqsave(&l1->lock,
-							  flags);
-					l1->hw->mr.
-					    fifo_rx_trans_enables[l1->
-								  st_num]
-					    |=
-					    ((bch->bchan ==
-					      1) ? 0x2 : 0x8);
-					l1->hw->mr.timer_usg_cnt++;
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 0 : 2)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_CON_HDLC, 0xf);	/* Transparent mode, 1 fill, connect ST */
-					Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
-					Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable TX interrupts */
-					Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
-					wait_busy(l1->hw);
-
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 1 : 3)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_CON_HDLC, 0xf);	/* Transparent mode, 1 fill, connect ST */
-					Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
-					Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable RX interrupts */
-					Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
-
-					Write_hfc8(l1->hw, R_ST_SEL,
-						   l1->st_num);
-					l1->hw->mr.r_ctrl0 |=
-					    (bch->bchan & 3);
-					Write_hfc8(l1->hw, A_ST_CTRL0,
-						   l1->hw->mr.r_ctrl0);
-					bch->mode = L1_MODE_TRANS;
-					spin_unlock_irqrestore(&l1->lock,
-							       flags);
-
-					bch->b_if.ifc.l1l2(&bch->b_if.ifc,
-							   PH_ACTIVATE |
-							   INDICATION,
-							   NULL);
-					break;
-
-				default:
-					if (bch->mode == L1_MODE_NULL)
-						break;
-					spin_lock_irqsave(&l1->lock,
-							  flags);
-					l1->hw->mr.
-					    fifo_slow_timer_service[l1->
-								    st_num]
-					    &=
-					    ~((bch->bchan ==
-					       1) ? 0x3 : 0xc);
-					l1->hw->mr.
-					    fifo_rx_trans_enables[l1->
-								  st_num]
-					    &=
-					    ~((bch->bchan ==
-					       1) ? 0x3 : 0xc);
-					l1->hw->mr.timer_usg_cnt--;
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 0 : 2)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable TX interrupts */
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, R_FIFO,
-						   (l1->st_num * 8 +
-						    ((bch->bchan ==
-						      1) ? 1 : 3)));
-					wait_busy(l1->hw);
-					Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable RX interrupts */
-					Write_hfc8(l1->hw, R_ST_SEL,
-						   l1->st_num);
-					l1->hw->mr.r_ctrl0 &=
-					    ~(bch->bchan & 3);
-					Write_hfc8(l1->hw, A_ST_CTRL0,
-						   l1->hw->mr.r_ctrl0);
-					spin_unlock_irqrestore(&l1->lock,
-							       flags);
-
-					bch->mode = L1_MODE_NULL;
-					bch->b_if.ifc.l1l2(&bch->b_if.ifc,
-							   PH_DEACTIVATE |
-							   INDICATION,
-							   NULL);
-					if (bch->tx_skb) {
-						dev_kfree_skb(bch->tx_skb);
-						bch->tx_skb = NULL;
-					}
-					if (bch->rx_skb) {
-						dev_kfree_skb(bch->rx_skb);
-						bch->rx_skb = NULL;
-					}
-					skb_queue_purge(&bch->tx_queue);
-					bch->tx_cnt = 0;
-					bch->rx_ptr = NULL;
-					break;
-			}
+	case (PH_ACTIVATE | REQUEST):
+	case (PH_DEACTIVATE | REQUEST):
+		if (!l1->enabled)
+			break;
+		if (pr == (PH_DEACTIVATE | REQUEST))
+			mode = L1_MODE_NULL;
+
+		switch (mode) {
+		case L1_MODE_HDLC:
+			spin_lock_irqsave(&l1->lock,
+					  flags);
+			l1->hw->mr.timer_usg_cnt++;
+			l1->hw->mr.
+				fifo_slow_timer_service[l1->
+							st_num]
+				|=
+				((bch->bchan ==
+				  1) ? 0x2 : 0x8);
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 0 : 2)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_CON_HDLC, 0xc);	/* HDLC mode, flag fill, connect ST */
+			Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
+			Write_hfc8(l1->hw, A_IRQ_MSK, 1);	/* enable TX interrupts for hdlc */
+			Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
+			wait_busy(l1->hw);
 
-			/* timer is only used when at least one b channel */
-			/* is set up to transparent mode */
-			if (l1->hw->mr.timer_usg_cnt) {
-				Write_hfc8(l1->hw, R_IRQMSK_MISC,
-					   M_TI_IRQMSK);
-			} else {
-				Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
-			}
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 1 : 3)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_CON_HDLC, 0xc);	/* HDLC mode, flag fill, connect ST */
+			Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
+			Write_hfc8(l1->hw, A_IRQ_MSK, 1);	/* enable RX interrupts for hdlc */
+			Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
+
+			Write_hfc8(l1->hw, R_ST_SEL,
+				   l1->st_num);
+			l1->hw->mr.r_ctrl0 |=
+				(bch->bchan & 3);
+			Write_hfc8(l1->hw, A_ST_CTRL0,
+				   l1->hw->mr.r_ctrl0);
+			bch->mode = L1_MODE_HDLC;
+			spin_unlock_irqrestore(&l1->lock,
+					       flags);
+
+			bch->b_if.ifc.l1l2(&bch->b_if.ifc,
+					   PH_ACTIVATE |
+					   INDICATION,
+					   NULL);
+			break;
 
+		case L1_MODE_TRANS:
+			spin_lock_irqsave(&l1->lock,
+					  flags);
+			l1->hw->mr.
+				fifo_rx_trans_enables[l1->
+						      st_num]
+				|=
+				((bch->bchan ==
+				  1) ? 0x2 : 0x8);
+			l1->hw->mr.timer_usg_cnt++;
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 0 : 2)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_CON_HDLC, 0xf);	/* Transparent mode, 1 fill, connect ST */
+			Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
+			Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable TX interrupts */
+			Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
+			wait_busy(l1->hw);
+
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 1 : 3)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_CON_HDLC, 0xf);	/* Transparent mode, 1 fill, connect ST */
+			Write_hfc8(l1->hw, A_SUBCH_CFG, 0);	/* 8 bits */
+			Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable RX interrupts */
+			Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);	/* reset fifo */
+
+			Write_hfc8(l1->hw, R_ST_SEL,
+				   l1->st_num);
+			l1->hw->mr.r_ctrl0 |=
+				(bch->bchan & 3);
+			Write_hfc8(l1->hw, A_ST_CTRL0,
+				   l1->hw->mr.r_ctrl0);
+			bch->mode = L1_MODE_TRANS;
+			spin_unlock_irqrestore(&l1->lock,
+					       flags);
+
+			bch->b_if.ifc.l1l2(&bch->b_if.ifc,
+					   PH_ACTIVATE |
+					   INDICATION,
+					   NULL);
 			break;
 
 		default:
-			printk(KERN_INFO
-			       "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
-			       pr);
+			if (bch->mode == L1_MODE_NULL)
+				break;
+			spin_lock_irqsave(&l1->lock,
+					  flags);
+			l1->hw->mr.
+				fifo_slow_timer_service[l1->
+							st_num]
+				&=
+				~((bch->bchan ==
+				   1) ? 0x3 : 0xc);
+			l1->hw->mr.
+				fifo_rx_trans_enables[l1->
+						      st_num]
+				&=
+				~((bch->bchan ==
+				   1) ? 0x3 : 0xc);
+			l1->hw->mr.timer_usg_cnt--;
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 0 : 2)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable TX interrupts */
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, R_FIFO,
+				   (l1->st_num * 8 +
+				    ((bch->bchan ==
+				      1) ? 1 : 3)));
+			wait_busy(l1->hw);
+			Write_hfc8(l1->hw, A_IRQ_MSK, 0);	/* disable RX interrupts */
+			Write_hfc8(l1->hw, R_ST_SEL,
+				   l1->st_num);
+			l1->hw->mr.r_ctrl0 &=
+				~(bch->bchan & 3);
+			Write_hfc8(l1->hw, A_ST_CTRL0,
+				   l1->hw->mr.r_ctrl0);
+			spin_unlock_irqrestore(&l1->lock,
+					       flags);
+
+			bch->mode = L1_MODE_NULL;
+			bch->b_if.ifc.l1l2(&bch->b_if.ifc,
+					   PH_DEACTIVATE |
+					   INDICATION,
+					   NULL);
+			if (bch->tx_skb) {
+				dev_kfree_skb(bch->tx_skb);
+				bch->tx_skb = NULL;
+			}
+			if (bch->rx_skb) {
+				dev_kfree_skb(bch->rx_skb);
+				bch->rx_skb = NULL;
+			}
+			skb_queue_purge(&bch->tx_queue);
+			bch->tx_cnt = 0;
+			bch->rx_ptr = NULL;
 			break;
+		}
+
+		/* timer is only used when at least one b channel */
+		/* is set up to transparent mode */
+		if (l1->hw->mr.timer_usg_cnt) {
+			Write_hfc8(l1->hw, R_IRQMSK_MISC,
+				   M_TI_IRQMSK);
+		} else {
+			Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
+		}
+
+		break;
+
+	default:
+		printk(KERN_INFO
+		       "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
+		       pr);
+		break;
 	}
 	if (!l1->enabled)
 		bch->b_if.ifc.l1l2(&bch->b_if.ifc,
@@ -742,7 +742,7 @@ rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 #ifdef HISAX_HFC4S8S_PCIMEM
 					Read_hfc8(l1p->hw, A_FIFO_DATA0);
 #else
-					fRead_hfc8(l1p->hw);
+				fRead_hfc8(l1p->hw);
 #endif
 
 				Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
@@ -760,7 +760,7 @@ rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 		while (z1 >= 4) {
 #ifdef HISAX_HFC4S8S_PCIMEM
 			*((unsigned long *) cp) =
-			    Read_hfc32(l1p->hw, A_FIFO_DATA0);
+				Read_hfc32(l1p->hw, A_FIFO_DATA0);
 #else
 			*((unsigned long *) cp) = fRead_hfc32(l1p->hw);
 #endif
@@ -772,7 +772,7 @@ rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 #ifdef HISAX_HFC4S8S_PCIMEM
 			*cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0);
 #else
-			*cp++ = fRead_hfc8(l1p->hw);
+		*cp++ = fRead_hfc8(l1p->hw);
 #endif
 
 		Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);	/* increment f counter */
@@ -866,10 +866,10 @@ rx_b_frame(struct hfc4s8s_btype *bch)
 		while (z1 >= 4) {
 #ifdef HISAX_HFC4S8S_PCIMEM
 			*((unsigned long *) bch->rx_ptr) =
-			    Read_hfc32(l1->hw, A_FIFO_DATA0);
+				Read_hfc32(l1->hw, A_FIFO_DATA0);
 #else
 			*((unsigned long *) bch->rx_ptr) =
-			    fRead_hfc32(l1->hw);
+				fRead_hfc32(l1->hw);
 #endif
 			bch->rx_ptr += 4;
 			z1 -= 4;
@@ -879,7 +879,7 @@ rx_b_frame(struct hfc4s8s_btype *bch)
 #ifdef HISAX_HFC4S8S_PCIMEM
 			*(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0);
 #else
-			*(bch->rx_ptr++) = fRead_hfc8(l1->hw);
+		*(bch->rx_ptr++) = fRead_hfc8(l1->hw);
 #endif
 
 		if (hdlc_complete) {
@@ -996,7 +996,7 @@ tx_b_frame(struct hfc4s8s_btype *bch)
 		if (bch->mode == L1_MODE_HDLC) {
 			hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
 			hdlc_num -=
-			    (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
+				(Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
 			if (hdlc_num < 0)
 				hdlc_num += 16;
 			if (hdlc_num >= 15)
@@ -1008,7 +1008,7 @@ tx_b_frame(struct hfc4s8s_btype *bch)
 			if (!(skb = skb_dequeue(&bch->tx_queue))) {
 				l1->hw->mr.fifo_slow_timer_service[l1->
 								   st_num]
-				    &= ~((bch->bchan == 1) ? 1 : 4);
+					&= ~((bch->bchan == 1) ? 1 : 4);
 				break;	/* list empty */
 			}
 			bch->tx_skb = skb;
@@ -1017,10 +1017,10 @@ tx_b_frame(struct hfc4s8s_btype *bch)
 
 		if (!hdlc_num)
 			l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
-			    ((bch->bchan == 1) ? 1 : 4);
+				((bch->bchan == 1) ? 1 : 4);
 		else
 			l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
-			    ~((bch->bchan == 1) ? 1 : 4);
+				~((bch->bchan == 1) ? 1 : 4);
 
 		max = Read_hfc16_stable(l1->hw, A_Z2);
 		max -= Read_hfc16(l1->hw, A_Z1);
@@ -1055,7 +1055,7 @@ tx_b_frame(struct hfc4s8s_btype *bch)
 #ifdef HISAX_HFC4S8S_PCIMEM
 			fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++);
 #else
-			fWrite_hfc8(l1->hw, *cp++);
+		fWrite_hfc8(l1->hw, *cp++);
 #endif
 
 		if (bch->tx_cnt >= skb->len) {
@@ -1106,8 +1106,8 @@ hfc4s8s_bh(struct work_struct *work)
 					Write_hfc8(l1p->hw, R_ST_SEL,
 						   l1p->st_num);
 					l1p->l1_state =
-					    Read_hfc8(l1p->hw,
-						      A_ST_RD_STA) & 0xf;
+						Read_hfc8(l1p->hw,
+							  A_ST_RD_STA) & 0xf;
 
 					if ((oldstate == 3)
 					    && (l1p->l1_state != 3))
@@ -1123,12 +1123,12 @@ hfc4s8s_bh(struct work_struct *work)
 						del_timer(&l1p->l1_timer);
 						if (l1p->l1_state == 3) {
 							l1p->d_if.ifc.
-							    l1l2(&l1p->
-								 d_if.ifc,
-								 PH_ACTIVATE
-								 |
-								 INDICATION,
-								 NULL);
+								l1l2(&l1p->
+								     d_if.ifc,
+								     PH_ACTIVATE
+								     |
+								     INDICATION,
+								     NULL);
 						}
 					} else {
 						/* allow transition */
@@ -1148,8 +1148,8 @@ hfc4s8s_bh(struct work_struct *work)
 					Write_hfc8(l1p->hw, R_ST_SEL,
 						   l1p->st_num);
 					l1p->l1_state =
-					    Read_hfc8(l1p->hw,
-						      A_ST_RD_STA) & 0xf;
+						Read_hfc8(l1p->hw,
+							  A_ST_RD_STA) & 0xf;
 
 					if (((l1p->l1_state == 3) &&
 					     ((oldstate == 7) ||
@@ -1165,26 +1165,26 @@ hfc4s8s_bh(struct work_struct *work)
 							del_timer(&l1p->
 								  l1_timer);
 							l1p->d_if.ifc.
-							    l1l2(&l1p->
-								 d_if.ifc,
-								 PH_ACTIVATE
-								 |
-								 INDICATION,
-								 NULL);
+								l1l2(&l1p->
+								     d_if.ifc,
+								     PH_ACTIVATE
+								     |
+								     INDICATION,
+								     NULL);
 							tx_d_frame(l1p);
 						}
 						if (l1p->l1_state == 3) {
 							if (oldstate != 3)
 								l1p->d_if.
-								    ifc.
-								    l1l2
-								    (&l1p->
-								     d_if.
-								     ifc,
-								     PH_DEACTIVATE
-								     |
-								     INDICATION,
-								     NULL);
+									ifc.
+									l1l2
+									(&l1p->
+									 d_if.
+									 ifc,
+									 PH_DEACTIVATE
+									 |
+									 INDICATION,
+									 NULL);
 						}
 					}
 					printk(KERN_INFO
@@ -1209,8 +1209,8 @@ hfc4s8s_bh(struct work_struct *work)
 			*fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
 			if (hw->fifo_sched_cnt <= 0) {
 				*fifo_stat |=
-				    hw->mr.fifo_slow_timer_service[l1p->
-								   st_num];
+					hw->mr.fifo_slow_timer_service[l1p->
+								       st_num];
 			}
 		}
 		/* ignore fifo 6 (TX E fifo) */
@@ -1288,10 +1288,10 @@ hfc4s8s_interrupt(int intno, void *dev_id)
 
 	/* Layer 1 State change */
 	hw->mr.r_irq_statech |=
-	    (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
+		(Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
 	if (!
 	    (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
-&& !hw->mr.r_irq_statech) {
+	    && !hw->mr.r_irq_statech) {
 #ifndef	HISAX_HFC4S8S_PCIMEM
 		SetRegAddr(hw, old_ioreg);
 #endif
@@ -1332,7 +1332,7 @@ hfc4s8s_interrupt(int intno, void *dev_id)
 /* reset the complete chip, don't release the chips irq but disable it */
 /***********************************************************************/
 static void
-chipreset(hfc4s8s_hw * hw)
+chipreset(hfc4s8s_hw *hw)
 {
 	u_long flags;
 
@@ -1361,7 +1361,7 @@ chipreset(hfc4s8s_hw * hw)
 /* disable/enable hardware in nt or te mode */
 /********************************************/
 static void
-hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode)
+hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode)
 {
 	u_long flags;
 	char if_name[40];
@@ -1468,7 +1468,7 @@ hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode)
 /* disable memory mapped ports / io ports */
 /******************************************/
 static void
-release_pci_ports(hfc4s8s_hw * hw)
+release_pci_ports(hfc4s8s_hw *hw)
 {
 	pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
 #ifdef HISAX_HFC4S8S_PCIMEM
@@ -1484,7 +1484,7 @@ release_pci_ports(hfc4s8s_hw * hw)
 /* enable memory mapped ports / io ports */
 /*****************************************/
 static void
-enable_pci_ports(hfc4s8s_hw * hw)
+enable_pci_ports(hfc4s8s_hw *hw)
 {
 #ifdef HISAX_HFC4S8S_PCIMEM
 	pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
@@ -1498,7 +1498,7 @@ enable_pci_ports(hfc4s8s_hw * hw)
 /* return 0 on success.              */
 /*************************************/
 static int __devinit
-setup_instance(hfc4s8s_hw * hw)
+setup_instance(hfc4s8s_hw *hw)
 {
 	int err = -EIO;
 	int i;
@@ -1575,7 +1575,7 @@ setup_instance(hfc4s8s_hw * hw)
 
 	return (0);
 
-      out:
+out:
 	hw->irq = 0;
 	release_pci_ports(hw);
 	kfree(hw);
@@ -1632,7 +1632,7 @@ hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		card_cnt++;
 	return (err);
 
-      out:
+out:
 	kfree(hw);
 	return (err);
 }
@@ -1660,10 +1660,10 @@ hfc4s8s_remove(struct pci_dev *pdev)
 }
 
 static struct pci_driver hfc4s8s_driver = {
-      .name	= "hfc4s8s_l1",
-      .probe	= hfc4s8s_probe,
-      .remove	= __devexit_p(hfc4s8s_remove),
-      .id_table	= hfc4s8s_ids,
+	.name	= "hfc4s8s_l1",
+	.probe	= hfc4s8s_probe,
+	.remove	= __devexit_p(hfc4s8s_remove),
+	.id_table	= hfc4s8s_ids,
 };
 
 /**********************/
@@ -1697,7 +1697,7 @@ hfc4s8s_module_init(void)
 #endif
 
 	return 0;
-      out:
+out:
 	return (err);
 }				/* hfc4s8s_init_hw */