diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2024-02-22 12:39:52 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-02-23 12:18:44 +0300 |
| commit | 6c725f33d67b53f2d302c2c4509deae953fc6ade (patch) | |
| tree | f7582a318a666944f799532945477eb3cf12ce56 /drivers/irqchip | |
| parent | b68d0ff529a939a118ec52f271be8cad5d99e79a (diff) | |
| download | linux-6c725f33d67b53f2d302c2c4509deae953fc6ade.tar.xz | |
irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode
The RISC-V INTC irqdomain is always the parent irqdomain of SiFive PLIC
so use riscv_get_intc_hwnode() to get the parent fwnode similar to other
RISC-V drivers which use local interrupts.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240222094006.1030709-5-apatel@ventanamicro.com
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-sifive-plic.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 299feefa4207..208fad76f560 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -423,6 +423,7 @@ static int plic_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; unsigned long plic_quirks = 0; struct plic_handler *handler; + struct irq_domain *domain; struct plic_priv *priv; bool cpuhp_setup; unsigned int cpu; @@ -502,11 +503,11 @@ static int plic_probe(struct platform_device *pdev) } /* Find parent domain and register chained handler */ - if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq = irq_of_parse_and_map(to_of_node(dev->fwnode), i); + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY); + if (!plic_parent_irq && domain) { + plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); if (plic_parent_irq) - irq_set_chained_handler(plic_parent_irq, - plic_handle_irq); + irq_set_chained_handler(plic_parent_irq, plic_handle_irq); } /* |