diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-06-03 21:36:34 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-06-03 21:36:34 +0300 |
| commit | 6f9b5ed8caddfbc94af8307c557ed57a8ec5c65c (patch) | |
| tree | dda90fb07a35fc07cf0cedc22f0f6be61b29cf53 /drivers/interconnect | |
| parent | 54c2cc79194c961a213c1d375fe3aa4165664cc4 (diff) | |
| parent | 90de6805267f8c79cd2b1a36805071e257c39b5c (diff) | |
| download | linux-6f9b5ed8caddfbc94af8307c557ed57a8ec5c65c.tar.xz | |
Merge tag 'char-misc-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc / other smaller driver subsystem updates from Greg KH:
"Here is the large set of char, misc, and other driver subsystem
updates for 5.19-rc1. The merge request for this has been delayed as I
wanted to get lots of linux-next testing due to some late arrivals of
changes for the habannalabs driver.
Highlights of this merge are:
- habanalabs driver updates for new hardware types and fixes and
other updates
- IIO driver tree merge which includes loads of new IIO drivers and
cleanups and additions
- PHY driver tree merge with new drivers and small updates to
existing ones
- interconnect driver tree merge with fixes and updates
- soundwire driver tree merge with some small fixes
- coresight driver tree merge with small fixes and updates
- mhi bus driver tree merge with lots of updates and new device
support
- firmware driver updates
- fpga driver updates
- lkdtm driver updates (with a merge conflict, more on that below)
- extcon driver tree merge with small updates
- lots of other tiny driver updates and fixes and cleanups, full
details in the shortlog.
All of these have been in linux-next for almost 2 weeks with no
reported problems"
* tag 'char-misc-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (387 commits)
habanalabs: use separate structure info for each error collect data
habanalabs: fix missing handle shift during mmap
habanalabs: remove hdev from hl_ctx_get args
habanalabs: do MMU prefetch as deferred work
habanalabs: order memory manager messages
habanalabs: return -EFAULT on copy_to_user error
habanalabs: use NULL for eventfd
habanalabs: update firmware header
habanalabs: add support for notification via eventfd
habanalabs: add topic to memory manager buffer
habanalabs: handle race in driver fini
habanalabs: add device memory scrub ability through debugfs
habanalabs: use unified memory manager for CB flow
habanalabs: unified memory manager new code for CB flow
habanalabs/gaudi: set arbitration timeout to a high value
habanalabs: add put by handle method to memory manager
habanalabs: hide memory manager page shift
habanalabs: Add separate poll interval value for protocol
habanalabs: use get_task_pid() to take PID
habanalabs: add prefetch flag to the MAP operation
...
Diffstat (limited to 'drivers/interconnect')
28 files changed, 4887 insertions, 600 deletions
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 91353e651a52..22adff5d7f53 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -110,6 +110,15 @@ config INTERCONNECT_QCOM_SC8180X This is a driver for the Qualcomm Network-on-Chip on sc8180x-based platforms. +config INTERCONNECT_QCOM_SC8280XP + tristate "Qualcomm SC8280XP interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SC8280XP-based + platforms. + config INTERCONNECT_QCOM_SDM660 tristate "Qualcomm SDM660 interconnect driver" depends on INTERCONNECT_QCOM @@ -137,6 +146,15 @@ config INTERCONNECT_QCOM_SDX55 This is a driver for the Qualcomm Network-on-Chip on sdx55-based platforms. +config INTERCONNECT_QCOM_SDX65 + tristate "Qualcomm SDX65 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sdx65-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index ceae9bb566c6..8d1fe9d38ac3 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -12,9 +12,11 @@ icc-rpmh-obj := icc-rpmh.o qnoc-sc7180-objs := sc7180.o qnoc-sc7280-objs := sc7280.o qnoc-sc8180x-objs := sc8180x.o +qnoc-sc8280xp-objs := sc8280xp.o qnoc-sdm660-objs := sdm660.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o +qnoc-sdx65-objs := sdx65.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o qnoc-sm8350-objs := sm8350.o @@ -33,9 +35,11 @@ obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o +obj-$(CONFIG_INTERCONNECT_QCOM_SC8280XP) += qnoc-sc8280xp.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o +obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 34125e8f8b60..fb013191c29b 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -274,20 +274,19 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) do_div(rate, qn->buswidth); rate = min_t(u64, rate, LONG_MAX); - if (qn->rate == rate) - return 0; - for (i = 0; i < qp->num_clks; i++) { + if (qp->bus_clk_rate[i] == rate) + continue; + ret = clk_set_rate(qp->bus_clks[i].clk, rate); if (ret) { pr_err("%s clk_set_rate error: %d\n", qp->bus_clks[i].id, ret); return ret; } + qp->bus_clk_rate[i] = rate; } - qn->rate = rate; - return 0; } @@ -301,7 +300,7 @@ int qnoc_probe(struct platform_device *pdev) const struct qcom_icc_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes; + struct qcom_icc_node * const *qnodes; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; @@ -332,6 +331,11 @@ int qnoc_probe(struct platform_device *pdev) if (!qp) return -ENOMEM; + qp->bus_clk_rate = devm_kcalloc(dev, cd_num, sizeof(*qp->bus_clk_rate), + GFP_KERNEL); + if (!qp->bus_clk_rate) + return -ENOMEM; + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); if (!data) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 26dad006034f..ebee9009301e 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -26,6 +26,7 @@ enum qcom_icc_type { * @type: the ICC provider type * @qos_offset: offset to QoS registers * @regmap: regmap for QoS registers read/write access + * @bus_clk_rate: bus clock rate in Hz */ struct qcom_icc_provider { struct icc_provider provider; @@ -33,6 +34,7 @@ struct qcom_icc_provider { enum qcom_icc_type type; struct regmap *regmap; unsigned int qos_offset; + u64 *bus_clk_rate; struct clk_bulk_data bus_clks[]; }; @@ -66,7 +68,6 @@ struct qcom_icc_qos { * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters - * @rate: current bus clock rate in Hz */ struct qcom_icc_node { unsigned char *name; @@ -77,11 +78,10 @@ struct qcom_icc_node { int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; - u64 rate; }; struct qcom_icc_desc { - struct qcom_icc_node **nodes; + struct qcom_icc_node * const *nodes; size_t num_nodes; const char * const *clocks; size_t num_clocks; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 2c8e12549804..3c40076eb5fb 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -189,7 +189,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes, *qn; + struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i, j; diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 4bfc060529ba..d29929461c17 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -22,7 +22,7 @@ struct qcom_icc_provider { struct icc_provider provider; struct device *dev; - struct qcom_icc_bcm **bcms; + struct qcom_icc_bcm * const *bcms; size_t num_bcms; struct bcm_voter *voter; }; @@ -112,9 +112,9 @@ struct qcom_icc_fabric { }; struct qcom_icc_desc { - struct qcom_icc_node **nodes; + struct qcom_icc_node * const *nodes; size_t num_nodes; - struct qcom_icc_bcm **bcms; + struct qcom_icc_bcm * const *bcms; size_t num_bcms; }; diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index 2f397a7c3322..5c4ba2f37c8e 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -1191,7 +1191,7 @@ static struct qcom_icc_node snoc_pcnoc_slv = { .links = snoc_pcnoc_slv_links, }; -static struct qcom_icc_node *msm8916_snoc_nodes[] = { +static struct qcom_icc_node * const msm8916_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, [MASTER_JPEG] = &mas_jpeg, [MASTER_MDP_PORT0] = &mas_mdp, @@ -1228,7 +1228,7 @@ static const struct regmap_config msm8916_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_snoc = { +static const struct qcom_icc_desc msm8916_snoc = { .type = QCOM_ICC_NOC, .nodes = msm8916_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), @@ -1236,7 +1236,7 @@ static struct qcom_icc_desc msm8916_snoc = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8916_bimc_nodes[] = { +static struct qcom_icc_node * const msm8916_bimc_nodes[] = { [BIMC_SNOC_MAS] = &bimc_snoc_mas, [MASTER_AMPSS_M0] = &mas_apss, [MASTER_GRAPHICS_3D] = &mas_gfx, @@ -1256,7 +1256,7 @@ static const struct regmap_config msm8916_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_bimc = { +static const struct qcom_icc_desc msm8916_bimc = { .type = QCOM_ICC_BIMC, .nodes = msm8916_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), @@ -1264,7 +1264,7 @@ static struct qcom_icc_desc msm8916_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { +static struct qcom_icc_node * const msm8916_pcnoc_nodes[] = { [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_DEHR] = &mas_dehr, [MASTER_LPASS] = &mas_audio, @@ -1325,7 +1325,7 @@ static const struct regmap_config msm8916_pcnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_pcnoc = { +static const struct qcom_icc_desc msm8916_pcnoc = { .type = QCOM_ICC_NOC, .nodes = msm8916_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index f9c2d7d3100d..63b31deea722 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1251,7 +1251,7 @@ static struct qcom_icc_node snoc_pcnoc_slv = { .links = snoc_pcnoc_slv_links, }; -static struct qcom_icc_node *msm8939_snoc_nodes[] = { +static struct qcom_icc_node * const msm8939_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_QDSS_ETR] = &mas_qdss_etr, @@ -1281,7 +1281,7 @@ static const struct regmap_config msm8939_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_snoc = { +static const struct qcom_icc_desc msm8939_snoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), @@ -1289,7 +1289,7 @@ static struct qcom_icc_desc msm8939_snoc = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { +static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = { [MASTER_VIDEO_P0] = &mas_video, [MASTER_JPEG] = &mas_jpeg, [MASTER_VFE] = &mas_vfe, @@ -1301,7 +1301,7 @@ static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { [SNOC_MM_INT_2] = &mm_int_2, }; -static struct qcom_icc_desc msm8939_snoc_mm = { +static const struct qcom_icc_desc msm8939_snoc_mm = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), @@ -1309,7 +1309,7 @@ static struct qcom_icc_desc msm8939_snoc_mm = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8939_bimc_nodes[] = { +static struct qcom_icc_node * const msm8939_bimc_nodes[] = { [BIMC_SNOC_MAS] = &bimc_snoc_mas, [MASTER_AMPSS_M0] = &mas_apss, [MASTER_GRAPHICS_3D] = &mas_gfx, @@ -1329,7 +1329,7 @@ static const struct regmap_config msm8939_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_bimc = { +static const struct qcom_icc_desc msm8939_bimc = { .type = QCOM_ICC_BIMC, .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), @@ -1337,7 +1337,7 @@ static struct qcom_icc_desc msm8939_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { +static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = { [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_DEHR] = &mas_dehr, [MASTER_LPASS] = &mas_audio, @@ -1400,7 +1400,7 @@ static const struct regmap_config msm8939_pcnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_pcnoc = { +static const struct qcom_icc_desc msm8939_pcnoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index da68ce375a89..6fa0ad90fc3d 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -220,7 +220,7 @@ struct msm8974_icc_node { }; struct msm8974_icc_desc { - struct msm8974_icc_node **nodes; + struct msm8974_icc_node * const *nodes; size_t num_nodes; }; @@ -244,7 +244,7 @@ DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); -static struct msm8974_icc_node *msm8974_bimc_nodes[] = { +static struct msm8974_icc_node * const msm8974_bimc_nodes[] = { [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0, [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1, [BIMC_MAS_MSS_PROC] = &mas_mss_proc, @@ -254,7 +254,7 @@ static struct msm8974_icc_node *msm8974_bimc_nodes[] = { [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2, }; -static struct msm8974_icc_desc msm8974_bimc = { +static const struct msm8974_icc_desc msm8974_bimc = { .nodes = msm8974_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes), }; @@ -297,7 +297,7 @@ DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); -static struct msm8974_icc_node *msm8974_cnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = { [CNOC_MAS_RPM_INST] = &mas_rpm_inst, [CNOC_MAS_RPM_DATA] = &mas_rpm_data, [CNOC_MAS_RPM_SYS] = &mas_rpm_sys, @@ -337,7 +337,7 @@ static struct msm8974_icc_node *msm8974_cnoc_nodes[] = { [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc, }; -static struct msm8974_icc_desc msm8974_cnoc = { +static const struct msm8974_icc_desc msm8974_cnoc = { .nodes = msm8974_cnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes), }; @@ -365,7 +365,7 @@ DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); -static struct msm8974_icc_node *msm8974_mnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = { [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d, [MNOC_MAS_JPEG] = &mas_jpeg, [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0, @@ -390,7 +390,7 @@ static struct msm8974_icc_node *msm8974_mnoc_nodes[] = { [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc, }; -static struct msm8974_icc_desc msm8974_mnoc = { +static const struct msm8974_icc_desc msm8974_mnoc = { .nodes = msm8974_mnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes), }; @@ -410,7 +410,7 @@ DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MS DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); -static struct msm8974_icc_node *msm8974_onoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_onoc_nodes[] = { [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc, [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem, [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem, @@ -425,7 +425,7 @@ static struct msm8974_icc_node *msm8974_onoc_nodes[] = { [OCMEM_SLV_OCMEM] = &slv_ocmem, }; -static struct msm8974_icc_desc msm8974_onoc = { +static const struct msm8974_icc_desc msm8974_onoc = { .nodes = msm8974_onoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes), }; @@ -458,7 +458,7 @@ DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC); DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); -static struct msm8974_icc_node *msm8974_pnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = { [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg, [PNOC_MAS_SDCC_1] = &mas_sdcc_1, [PNOC_MAS_SDCC_3] = &mas_sdcc_3, @@ -488,7 +488,7 @@ static struct msm8974_icc_node *msm8974_pnoc_nodes[] = { [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc, }; -static struct msm8974_icc_desc msm8974_pnoc = { +static const struct msm8974_icc_desc msm8974_pnoc = { .nodes = msm8974_pnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes), }; @@ -518,7 +518,7 @@ DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); -static struct msm8974_icc_node *msm8974_snoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_snoc_nodes[] = { [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb, [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam, [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg, @@ -545,7 +545,7 @@ static struct msm8974_icc_node *msm8974_snoc_nodes[] = { [SNOC_SLV_QDSS_STM] = &slv_qdss_stm, }; -static struct msm8974_icc_desc msm8974_snoc = { +static const struct msm8974_icc_desc msm8974_snoc = { .nodes = msm8974_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes), }; @@ -648,7 +648,7 @@ static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) static int msm8974_icc_probe(struct platform_device *pdev) { const struct msm8974_icc_desc *desc; - struct msm8974_icc_node **qnodes; + struct msm8974_icc_node * const *qnodes; struct msm8974_icc_provider *qp; struct device *dev = &pdev->dev; struct icc_onecell_data *data; diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index 499e11fbbd2e..c2903ae3b3bc 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -1796,7 +1796,7 @@ static struct qcom_icc_node slv_srvc_snoc = { .qos.qos_mode = NOC_QOS_MODE_INVALID }; -static struct qcom_icc_node *a0noc_nodes[] = { +static struct qcom_icc_node * const a0noc_nodes[] = { [MASTER_PCIE_0] = &mas_pcie_0, [MASTER_PCIE_1] = &mas_pcie_1, [MASTER_PCIE_2] = &mas_pcie_2 @@ -1820,7 +1820,7 @@ static const struct qcom_icc_desc msm8996_a0noc = { .regmap_cfg = &msm8996_a0noc_regmap_config }; -static struct qcom_icc_node *a1noc_nodes[] = { +static struct qcom_icc_node * const a1noc_nodes[] = { [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc, [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc @@ -1841,7 +1841,7 @@ static const struct qcom_icc_desc msm8996_a1noc = { .regmap_cfg = &msm8996_a1noc_regmap_config }; -static struct qcom_icc_node *a2noc_nodes[] = { +static struct qcom_icc_node * const a2noc_nodes[] = { [MASTER_USB3] = &mas_usb3, [MASTER_IPA] = &mas_ipa, [MASTER_UFS] = &mas_ufs @@ -1862,7 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = { .regmap_cfg = &msm8996_a2noc_regmap_config }; -static struct qcom_icc_node *bimc_nodes[] = { +static struct qcom_icc_node * const bimc_nodes[] = { [MASTER_AMPSS_M0] = &mas_apps_proc, [MASTER_GRAPHICS_3D] = &mas_oxili, [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, @@ -1888,7 +1888,7 @@ static const struct qcom_icc_desc msm8996_bimc = { .regmap_cfg = &msm8996_bimc_regmap_config }; -static struct qcom_icc_node *cnoc_nodes[] = { +static struct qcom_icc_node * const cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc, @@ -1946,7 +1946,7 @@ static const struct qcom_icc_desc msm8996_cnoc = { .regmap_cfg = &msm8996_cnoc_regmap_config }; -static struct qcom_icc_node *mnoc_nodes[] = { +static struct qcom_icc_node * const mnoc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, [MASTER_CPP] = &mas_cpp, [MASTER_JPEG] = &mas_jpeg, @@ -2001,7 +2001,7 @@ static const struct qcom_icc_desc msm8996_mnoc = { .regmap_cfg = &msm8996_mnoc_regmap_config }; -static struct qcom_icc_node *pnoc_nodes[] = { +static struct qcom_icc_node * const pnoc_nodes[] = { [MASTER_SNOC_PNOC] = &mas_snoc_pnoc, [MASTER_SDCC_1] = &mas_sdcc_1, [MASTER_SDCC_2] = &mas_sdcc_2, @@ -2037,7 +2037,7 @@ static const struct qcom_icc_desc msm8996_pnoc = { .regmap_cfg = &msm8996_pnoc_regmap_config }; -static struct qcom_icc_node *snoc_nodes[] = { +static struct qcom_icc_node * const snoc_nodes[] = { [MASTER_HMSS] = &mas_hmss, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_SNOC_CFG] = &mas_snoc_cfg, diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index eec13099a6a3..4198656f4e59 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -67,7 +67,7 @@ struct qcom_osm_l3_node { }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node **nodes; + const struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; @@ -86,7 +86,7 @@ struct qcom_osm_l3_desc { DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3); DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16); -static const struct qcom_osm_l3_node *sdm845_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3, [SLAVE_OSM_L3] = &sdm845_osm_l3, }; @@ -102,7 +102,7 @@ static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = { DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3); DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16); -static const struct qcom_osm_l3_node *sc7180_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3, [SLAVE_OSM_L3] = &sc7180_osm_l3, }; @@ -118,7 +118,7 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); -static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, }; @@ -134,7 +134,7 @@ static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); -static const struct qcom_osm_l3_node *sc8180x_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3, [SLAVE_OSM_L3] = &sc8180x_osm_l3, }; @@ -150,7 +150,7 @@ static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = { DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3); DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32); -static const struct qcom_osm_l3_node *sm8150_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3, [SLAVE_OSM_L3] = &sm8150_osm_l3, }; @@ -166,7 +166,7 @@ static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = { DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3); DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32); -static const struct qcom_osm_l3_node *sm8250_epss_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3, [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3, }; @@ -228,7 +228,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node **qnodes; + const struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 74404e0b2080..0da612d6398c 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1174,7 +1174,7 @@ static struct qcom_icc_node slv_anoc_snoc = { }; /* NoC descriptors */ -static struct qcom_icc_node *qcm2290_bimc_nodes[] = { +static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { [MASTER_APPSS_PROC] = &mas_appss_proc, [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, @@ -1193,7 +1193,7 @@ static const struct regmap_config qcm2290_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_bimc = { +static const struct qcom_icc_desc qcm2290_bimc = { .type = QCOM_ICC_BIMC, .nodes = qcm2290_bimc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), @@ -1202,7 +1202,7 @@ static struct qcom_icc_desc qcm2290_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *qcm2290_cnoc_nodes[] = { +static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_BIMC_CFG] = &slv_bimc_cfg, @@ -1248,14 +1248,14 @@ static const struct regmap_config qcm2290_cnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_cnoc = { +static const struct qcom_icc_desc qcm2290_cnoc = { .type = QCOM_ICC_NOC, .nodes = qcm2290_cnoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), .regmap_cfg = &qcm2290_cnoc_regmap_config, }; -static struct qcom_icc_node *qcm2290_snoc_nodes[] = { +static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, [MASTER_SNOC_CFG] = &mas_snoc_cfg, [MASTER_TIC] = &mas_tic, @@ -1289,7 +1289,7 @@ static const struct regmap_config qcm2290_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_snoc = { +static const struct qcom_icc_desc qcm2290_snoc = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_snoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), @@ -1298,25 +1298,25 @@ static struct qcom_icc_desc qcm2290_snoc = { .qos_offset = 0x15000, }; -static struct qcom_icc_node *qcm2290_qup_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { [MASTER_QUP_CORE_0] = &mas_qup_core_0, [SLAVE_QUP_CORE_0] = &slv_qup_core_0 }; -static struct qcom_icc_desc qcm2290_qup_virt = { +static const struct qcom_icc_desc qcm2290_qup_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_qup_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), }; -static struct qcom_icc_node *qcm2290_mmnrt_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { [MASTER_CAMNOC_SF] = &mas_camnoc_sf, [MASTER_VIDEO_P0] = &mas_video_p0, [MASTER_VIDEO_PROC] = &mas_video_proc, [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, }; -static struct qcom_icc_desc qcm2290_mmnrt_virt = { +static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmnrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), @@ -1324,13 +1324,13 @@ static struct qcom_icc_desc qcm2290_mmnrt_virt = { .qos_offset = 0x15000, }; -static struct qcom_icc_node *qcm2290_mmrt_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { [MASTER_CAMNOC_HF] = &mas_camnoc_hf, [MASTER_MDP0] = &mas_mdp0, [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, }; -static struct qcom_icc_desc qcm2290_mmrt_virt = { +static const struct qcom_icc_desc qcm2290_mmrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 416c8bff8efa..fae155344332 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -974,7 +974,7 @@ static struct qcom_icc_node slv_lpass = { .slv_rpm_id = -1, }; -static struct qcom_icc_node *qcs404_bimc_nodes[] = { +static struct qcom_icc_node * const qcs404_bimc_nodes[] = { [MASTER_AMPSS_M0] = &mas_apps_proc, [MASTER_OXILI] = &mas_oxili, [MASTER_MDP_PORT0] = &mas_mdp, @@ -984,12 +984,12 @@ static struct qcom_icc_node *qcs404_bimc_nodes[] = { [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, }; -static struct qcom_icc_desc qcs404_bimc = { +static const struct qcom_icc_desc qcs404_bimc = { .nodes = qcs404_bimc_nodes, .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes), }; -static struct qcom_icc_node *qcs404_pcnoc_nodes[] = { +static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = { [MASTER_SPDM] = &mas_spdm, [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_BLSP_2] = &mas_blsp_2, @@ -1038,12 +1038,12 @@ static struct qcom_icc_node *qcs404_pcnoc_nodes[] = { [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc, }; -static struct qcom_icc_desc qcs404_pcnoc = { +static const struct qcom_icc_desc qcs404_pcnoc = { .nodes = qcs404_pcnoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes), }; -static struct qcom_icc_node *qcs404_snoc_nodes[] = { +static struct qcom_icc_node * const qcs404_snoc_nodes[] = { [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_BIMC_SNOC] = &mas_bimc_snoc, [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc, @@ -1066,7 +1066,7 @@ static struct qcom_icc_node *qcs404_snoc_nodes[] = { [SLAVE_LPASS] = &slv_lpass, }; -static struct qcom_icc_desc qcs404_snoc = { +static const struct qcom_icc_desc qcs404_snoc = { .nodes = qcs404_snoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes), }; diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 5f7c0f85fa8e..35cd448efdfb 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -178,11 +178,11 @@ DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QSPI] = &qhm_qspi, [MASTER_QUP_0] = &qhm_qup_0, @@ -193,18 +193,18 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sc7180_aggre1_noc = { +static const struct qcom_icc_desc sc7180_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_1] = &qhm_qup_1, @@ -216,56 +216,56 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sc7180_aggre2_noc = { +static const struct qcom_icc_desc sc7180_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, }; -static struct qcom_icc_desc sc7180_camnoc_virt = { +static const struct qcom_icc_desc sc7180_camnoc_virt = { .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, &bcm_co3, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [MASTER_NPU_PROC] = &qxm_npu_dsp, [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, }; -static struct qcom_icc_desc sc7180_compute_noc = { +static const struct qcom_icc_desc sc7180_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, &bcm_cn1, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SNOC_CNOC] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, @@ -321,32 +321,32 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sc7180_config_noc = { +static const struct qcom_icc_desc sc7180_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, [SLAVE_LLCC_CFG] = &qhs_llcc, }; -static struct qcom_icc_desc sc7180_dc_noc = { +static const struct qcom_icc_desc sc7180_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_APPSS_PROC] = &acm_apps0, [MASTER_SYS_TCU] = &acm_sys_tcu, [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, @@ -362,7 +362,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; -static struct qcom_icc_desc sc7180_gem_noc = { +static const struct qcom_icc_desc sc7180_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -374,25 +374,25 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, }; -static struct qcom_icc_desc sc7180_mc_virt = { +static const struct qcom_icc_desc sc7180_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -406,14 +406,14 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sc7180_mmss_noc = { +static const struct qcom_icc_desc sc7180_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_node *npu_noc_nodes[] = { +static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, @@ -427,30 +427,30 @@ static struct qcom_icc_node *npu_noc_nodes[] = { [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, }; -static struct qcom_icc_desc sc7180_npu_noc = { +static const struct qcom_icc_desc sc7180_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), }; -static struct qcom_icc_bcm *qup_virt_bcms[] = { +static struct qcom_icc_bcm * const qup_virt_bcms[] = { &bcm_qup0, }; -static struct qcom_icc_node *qup_virt_nodes[] = { +static struct qcom_icc_node * const qup_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup_core_master_1, [MASTER_QUP_CORE_1] = &qup_core_master_2, [SLAVE_QUP_CORE_0] = &qup_core_slave_1, [SLAVE_QUP_CORE_1] = &qup_core_slave_2, }; -static struct qcom_icc_desc sc7180_qup_virt = { +static const struct qcom_icc_desc sc7180_qup_virt = { .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, .num_bcms = ARRAY_SIZE(qup_virt_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, @@ -461,7 +461,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn12, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, @@ -478,7 +478,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sc7180_system_noc = { +static const struct qcom_icc_desc sc7180_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index f8b34f6cbb0d..971f538bc98a 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1476,13 +1476,13 @@ static struct qcom_icc_bcm bcm_sn14 = { .nodes = { &qns_pcie_mem_noc }, }; -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn5, &bcm_sn6, &bcm_sn14, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_1] = &qhm_qup1, @@ -1500,18 +1500,18 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sc7280_aggre1_noc = { +static const struct qcom_icc_desc sc7280_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, @@ -1522,38 +1522,38 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sc7280_aggre2_noc = { +static const struct qcom_icc_desc sc7280_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *clk_virt_bcms[] = { +static struct qcom_icc_bcm * const clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, }; -static struct qcom_icc_node *clk_virt_nodes[] = { +static struct qcom_icc_node * const clk_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [SLAVE_QUP_CORE_0] = &qup0_core_slave, [SLAVE_QUP_CORE_1] = &qup1_core_slave, }; -static struct qcom_icc_desc sc7280_clk_virt = { +static const struct qcom_icc_desc sc7280_clk_virt = { .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), }; -static struct qcom_icc_bcm *cnoc2_bcms[] = { +static struct qcom_icc_bcm * const cnoc2_bcms[] = { &bcm_cn1, &bcm_cn2, }; -static struct qcom_icc_node *cnoc2_nodes[] = { +static struct qcom_icc_node * const cnoc2_nodes[] = { [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, @@ -1603,21 +1603,21 @@ static struct qcom_icc_node *cnoc2_nodes[] = { [SLAVE_SNOC_CFG] = &qns_snoc_cfg, }; -static struct qcom_icc_desc sc7280_cnoc2 = { +static const struct qcom_icc_desc sc7280_cnoc2 = { .nodes = cnoc2_nodes, .num_nodes = ARRAY_SIZE(cnoc2_nodes), .bcms = cnoc2_bcms, .num_bcms = ARRAY_SIZE(cnoc2_bcms), }; -static struct qcom_icc_bcm *cnoc3_bcms[] = { +static struct qcom_icc_bcm * const cnoc3_bcms[] = { &bcm_cn0, &bcm_cn1, &bcm_sn3, &bcm_sn4, }; -static struct qcom_icc_node *cnoc3_nodes[] = { +static struct qcom_icc_node * const cnoc3_nodes[] = { [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, @@ -1635,37 +1635,37 @@ static struct qcom_icc_node *cnoc3_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sc7280_cnoc3 = { +static const struct qcom_icc_desc sc7280_cnoc3 = { .nodes = cnoc3_nodes, .num_nodes = ARRAY_SIZE(cnoc3_nodes), .bcms = cnoc3_bcms, .num_bcms = ARRAY_SIZE(cnoc3_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; -static struct qcom_icc_desc sc7280_dc_noc = { +static const struct qcom_icc_desc sc7280_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -1687,17 +1687,17 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, }; -static struct qcom_icc_desc sc7280_gem_noc = { +static const struct qcom_icc_desc sc7280_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, @@ -1707,38 +1707,38 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sc7280_lpass_ag_noc = { +static const struct qcom_icc_desc sc7280_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, }; -static struct qcom_icc_desc sc7280_mc_virt = { +static const struct qcom_icc_desc sc7280_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm4, &bcm_mm5, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, [MASTER_VIDEO_P0] = &qnm_video0, [MASTER_VIDEO_PROC] = &qnm_video_cpu, @@ -1751,40 +1751,40 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sc7280_mmss_noc = { +static const struct qcom_icc_desc sc7280_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, &bcm_co3, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sc7280_nsp_noc = { +static const struct qcom_icc_desc sc7280_nsp_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn2, &bcm_sn7, &bcm_sn8, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [MASTER_SNOC_CFG] = &qnm_snoc_cfg, @@ -1795,7 +1795,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sc7280_system_noc = { +static const struct qcom_icc_desc sc7280_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index e9adf05b9330..8e32ca958824 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -15,229 +15,1611 @@ #include "icc-rpmh.h" #include "sc8180x.h" -DEFINE_QNODE(mas_qhm_a1noc_cfg, SC8180X_MASTER_A1NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(mas_xm_ufs_card, SC8180X_MASTER_UFS_CARD, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_ufs_g4, SC8180X_MASTER_UFS_GEN4, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_ufs_mem, SC8180X_MASTER_UFS_MEM, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_0, SC8180X_MASTER_USB3, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_1, SC8180X_MASTER_USB3_1, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_2, SC8180X_MASTER_USB3_2, 1, 16, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_a2noc_cfg, SC8180X_MASTER_A2NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(mas_qhm_qdss_bam, SC8180X_MASTER_QDSS_BAM, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qspi, SC8180X_MASTER_QSPI_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qspi1, SC8180X_MASTER_QSPI_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup0, SC8180X_MASTER_QUP_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup1, SC8180X_MASTER_QUP_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup2, SC8180X_MASTER_QUP_2, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_sensorss_ahb, SC8180X_MASTER_SENSORS_AHB, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_crypto, SC8180X_MASTER_CRYPTO_CORE_0, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_ipa, SC8180X_MASTER_IPA, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_emac, SC8180X_MASTER_EMAC, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_pcie3_0, SC8180X_MASTER_PCIE, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_1, SC8180X_MASTER_PCIE_1, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_2, SC8180X_MASTER_PCIE_2, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_3, SC8180X_MASTER_PCIE_3, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_qdss_etr, SC8180X_MASTER_QDSS_ETR, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_sdc2, SC8180X_MASTER_SDCC_2, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_sdc4, SC8180X_MASTER_SDCC_4, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_camnoc_hf0_uncomp, SC8180X_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qxm_camnoc_hf1_uncomp, SC8180X_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qxm_camnoc_sf_uncomp, SC8180X_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qnm_npu, SC8180X_MASTER_NPU, 1, 32, SC8180X_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(mas_qnm_snoc, SC8180X_SNOC_CNOC_MAS, 1, 8, SC8180X_SLAVE_TLMM_SOUTH, SC8180X_SLAVE_CDSP_CFG, SC8180X_SLAVE_SPSS_CFG, SC8180X_SLAVE_CAMERA_CFG, SC8180X_SLAVE_SDCC_4, SC8180X_SLAVE_AHB2PHY_CENTER, SC8180X_SLAVE_SDCC_2, SC8180X_SLAVE_PCIE_2_CFG, SC8180X_SLAVE_CNOC_MNOC_CFG, SC8180X_SLAVE_EMAC_CFG, SC8180X_SLAVE_QSPI_0, SC8180X_SLAVE_QSPI_1, SC8180X_SLAVE_TLMM_EAST, SC8180X_SLAVE_SNOC_CFG, SC8180X_SLAVE_AHB2PHY_EAST, SC8180X_SLAVE_GLM, SC8180X_SLAVE_PDM, SC8180X_SLAVE_PCIE_1_CFG, SC8180X_SLAVE_A2NOC_CFG, SC8180X_SLAVE_QDSS_CFG, SC8180X_SLAVE_DISPLAY_CFG, SC8180X_SLAVE_TCSR, SC8180X_SLAVE_UFS_MEM_0_CFG, SC8180X_SLAVE_CNOC_DDRSS, SC8180X_SLAVE_PCIE_0_CFG, SC8180X_SLAVE_QUP_1, SC8180X_SLAVE_QUP_2, SC8180X_SLAVE_NPU_CFG, SC8180X_SLAVE_CRYPTO_0_CFG, SC8180X_SLAVE_GRAPHICS_3D_CFG, SC8180X_SLAVE_VENUS_CFG, SC8180X_SLAVE_TSIF, SC8180X_SLAVE_IPA_CFG, SC8180X_SLAVE_CLK_CTL, SC8180X_SLAVE_SECURITY, SC8180X_SLAVE_AOP, SC8180X_SLAVE_AHB2PHY_WEST, SC8180X_SLAVE_AHB2PHY_SOUTH, SC8180X_SLAVE_SERVICE_CNOC, SC8180X_SLAVE_UFS_CARD_CFG, SC8180X_SLAVE_USB3_1, SC8180X_SLAVE_USB3_2, SC8180X_SLAVE_PCIE_3_CFG, SC8180X_SLAVE_RBCPR_CX_CFG, SC8180X_SLAVE_TLMM_WEST, SC8180X_SLAVE_A1NOC_CFG, SC8180X_SLAVE_AOSS, SC8180X_SLAVE_PRNG, SC8180X_SLAVE_VSENSE_CTRL_CFG, SC8180X_SLAVE_QUP_0, SC8180X_SLAVE_USB3, SC8180X_SLAVE_RBCPR_MMCX_CFG, SC8180X_SLAVE_PIMEM_CFG, SC8180X_SLAVE_UFS_MEM_1_CFG, SC8180X_SLAVE_RBCPR_MX_CFG, SC8180X_SLAVE_IMEM_CFG); -DEFINE_QNODE(mas_qhm_cnoc_dc_noc, SC8180X_MASTER_CNOC_DC_NOC, 1, 4, SC8180X_SLAVE_LLCC_CFG, SC8180X_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(mas_acm_apps, SC8180X_MASTER_AMPSS_M0, 4, 64, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_acm_gpu_tcu, SC8180X_MASTER_GPU_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_acm_sys_tcu, SC8180X_MASTER_SYS_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qhm_gemnoc_cfg, SC8180X_MASTER_GEM_NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_GEM_NOC_1, SC8180X_SLAVE_SERVICE_GEM_NOC, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(mas_qnm_cmpnoc, SC8180X_MASTER_COMPUTE_NOC, 2, 32, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_gpu, SC8180X_MASTER_GRAPHICS_3D, 4, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_mnoc_hf, SC8180X_MASTER_MNOC_HF_MEM_NOC, 2, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qnm_mnoc_sf, SC8180X_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_pcie, SC8180X_MASTER_GEM_NOC_PCIE_SNOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_snoc_gc, SC8180X_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qnm_snoc_sf, SC8180X_MASTER_SNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qxm_ecc, SC8180X_MASTER_ECC, 2, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_ipa_core_master, SC8180X_MASTER_IPA_CORE, 1, 8, SC8180X_SLAVE_IPA_CORE); -DEFINE_QNODE(mas_llcc_mc, SC8180X_MASTER_LLCC, 8, 4, SC8180X_SLAVE_EBI_CH0); -DEFINE_QNODE(mas_qhm_mnoc_cfg, SC8180X_MASTER_CNOC_MNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(mas_qxm_camnoc_hf0, SC8180X_MASTER_CAMNOC_HF0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_camnoc_hf1, SC8180X_MASTER_CAMNOC_HF1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_camnoc_sf, SC8180X_MASTER_CAMNOC_SF, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_mdp0, SC8180X_MASTER_MDP_PORT0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_mdp1, SC8180X_MASTER_MDP_PORT1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_rot, SC8180X_MASTER_ROTATOR, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus0, SC8180X_MASTER_VIDEO_P0, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus1, SC8180X_MASTER_VIDEO_P1, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus_arm9, SC8180X_MASTER_VIDEO_PROC, 1, 8, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qhm_snoc_cfg, SC8180X_MASTER_SNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(mas_qnm_aggre1_noc, SC8180X_A1NOC_SNOC_MAS, 1, 32, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qnm_aggre2_noc, SC8180X_A2NOC_SNOC_MAS, 1, 16, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_PCIE_3, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SLAVE_PCIE_2, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_PCIE_0, SC8180X_SLAVE_PCIE_1, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qnm_gemnoc, SC8180X_MASTER_GEM_NOC_SNOC, 1, 8, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qxm_pimem, SC8180X_MASTER_PIMEM, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); -DEFINE_QNODE(mas_xm_gic, SC8180X_MASTER_GIC, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); -DEFINE_QNODE(slv_qns_a1noc_snoc, SC8180X_A1NOC_SNOC_SLV, 1, 32, SC8180X_A1NOC_SNOC_MAS); -DEFINE_QNODE(slv_srvc_aggre1_noc, SC8180X_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(slv_qns_a2noc_snoc, SC8180X_A2NOC_SNOC_SLV, 1, 16, SC8180X_A2NOC_SNOC_MAS); -DEFINE_QNODE(slv_qns_pcie_mem_noc, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, 1, 32, SC8180X_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(slv_srvc_aggre2_noc, SC8180X_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(slv_qns_camnoc_uncomp, SC8180X_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(slv_qns_cdsp_mem_noc, SC8180X_SLAVE_CDSP_MEM_NOC, 2, 32, SC8180X_MASTER_COMPUTE_NOC); -DEFINE_QNODE(slv_qhs_a1_noc_cfg, SC8180X_SLAVE_A1NOC_CFG, 1, 4, SC8180X_MASTER_A1NOC_CFG); -DEFINE_QNODE(slv_qhs_a2_noc_cfg, SC8180X_SLAVE_A2NOC_CFG, 1, 4, SC8180X_MASTER_A2NOC_CFG); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_center, SC8180X_SLAVE_AHB2PHY_CENTER, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_east, SC8180X_SLAVE_AHB2PHY_EAST, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_west, SC8180X_SLAVE_AHB2PHY_WEST, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_south, SC8180X_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(slv_qhs_aop, SC8180X_SLAVE_AOP, 1, 4); -DEFINE_QNODE(slv_qhs_aoss, SC8180X_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(slv_qhs_camera_cfg, SC8180X_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_clk_ctl, SC8180X_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(slv_qhs_compute_dsp, SC8180X_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_cx, SC8180X_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_mmcx, SC8180X_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_mx, SC8180X_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_crypto0_cfg, SC8180X_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ddrss_cfg, SC8180X_SLAVE_CNOC_DDRSS, 1, 4, SC8180X_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(slv_qhs_display_cfg, SC8180X_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_emac_cfg, SC8180X_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_glm, SC8180X_SLAVE_GLM, 1, 4); -DEFINE_QNODE(slv_qhs_gpuss_cfg, SC8180X_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(slv_qhs_imem_cfg, SC8180X_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ipa, SC8180X_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_mnoc_cfg, SC8180X_SLAVE_CNOC_MNOC_CFG, 1, 4, SC8180X_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(slv_qhs_npu_cfg, SC8180X_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie0_cfg, SC8180X_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie1_cfg, SC8180X_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie2_cfg, SC8180X_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie3_cfg, SC8180X_SLAVE_PCIE_3_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pdm, SC8180X_SLAVE_PDM, 1, 4); -DEFINE_QNODE(slv_qhs_pimem_cfg, SC8180X_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_prng, SC8180X_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(slv_qhs_qdss_cfg, SC8180X_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_qspi_0, SC8180X_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(slv_qhs_qspi_1, SC8180X_SLAVE_QSPI_1, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_east0, SC8180X_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_east1, SC8180X_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_west, SC8180X_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(slv_qhs_sdc2, SC8180X_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(slv_qhs_sdc4, SC8180X_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(slv_qhs_security, SC8180X_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(slv_qhs_snoc_cfg, SC8180X_SLAVE_SNOC_CFG, 1, 4, SC8180X_MASTER_SNOC_CFG); -DEFINE_QNODE(slv_qhs_spss_cfg, SC8180X_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_tcsr, SC8180X_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_east, SC8180X_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_south, SC8180X_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_west, SC8180X_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(slv_qhs_tsif, SC8180X_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_card_cfg, SC8180X_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_mem0_cfg, SC8180X_SLAVE_UFS_MEM_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_mem1_cfg, SC8180X_SLAVE_UFS_MEM_1_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_0, SC8180X_SLAVE_USB3, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_1, SC8180X_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_2, SC8180X_SLAVE_USB3_2, 1, 4); -DEFINE_QNODE(slv_qhs_venus_cfg, SC8180X_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_vsense_ctrl_cfg, SC8180X_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(slv_srvc_cnoc, SC8180X_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(slv_qhs_gemnoc, SC8180X_SLAVE_GEM_NOC_CFG, 1, 4, SC8180X_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(slv_qhs_llcc, SC8180X_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_mdsp_ms_mpu_cfg, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(slv_qns_ecc, SC8180X_SLAVE_ECC, 1, 32); -DEFINE_QNODE(slv_qns_gem_noc_snoc, SC8180X_SLAVE_GEM_NOC_SNOC, 1, 8, SC8180X_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(slv_qns_llcc, SC8180X_SLAVE_LLCC, 8, 16, SC8180X_MASTER_LLCC); -DEFINE_QNODE(slv_srvc_gemnoc, SC8180X_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(slv_srvc_gemnoc1, SC8180X_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(slv_ipa_core_slave, SC8180X_SLAVE_IPA_CORE, 1, 8); -DEFINE_QNODE(slv_ebi, SC8180X_SLAVE_EBI_CH0, 8, 4); -DEFINE_QNODE(slv_qns2_mem_noc, SC8180X_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC8180X_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(slv_qns_mem_noc_hf, SC8180X_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SC8180X_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(slv_srvc_mnoc, SC8180X_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(slv_qhs_apss, SC8180X_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(slv_qns_cnoc, SC8180X_SNOC_CNOC_SLV, 1, 8, SC8180X_SNOC_CNOC_MAS); -DEFINE_QNODE(slv_qns_gemnoc_gc, SC8180X_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC8180X_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(slv_qns_gemnoc_sf, SC8180X_SLAVE_SNOC_GEM_NOC_SF, 1, 32, SC8180X_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(slv_qxs_imem, SC8180X_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(slv_qxs_pimem, SC8180X_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(slv_srvc_snoc, SC8180X_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(slv_xs_pcie_0, SC8180X_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(slv_xs_pcie_1, SC8180X_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(slv_xs_pcie_2, SC8180X_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(slv_xs_pcie_3, SC8180X_SLAVE_PCIE_3, 1, 8); -DEFINE_QNODE(slv_xs_qdss_stm, SC8180X_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(slv_xs_sys_tcu_cfg, SC8180X_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi); -DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi); -DEFINE_QBCM(bcm_sh0, "SH0", false, &slv_qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf); -DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); -DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qhm_qup0, &mas_qhm_qup1, &mas_qhm_qup2); -DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &mas_acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", false, &slv_qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn1, "SN1", false, &slv_qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &slv_qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &mas_qnm_npu); -DEFINE_QBCM(bcm_ip0, "IP0", false, &slv_ipa_core_slave); -DEFINE_QBCM(bcm_sn3, "SN3", false, &slv_srvc_aggre1_noc, &slv_qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &slv_qxs_pimem); -DEFINE_QBCM(bcm_sn8, "SN8", false, &slv_xs_pcie_0, &slv_xs_pcie_1, &slv_xs_pcie_2, &slv_xs_pcie_3); -DEFINE_QBCM(bcm_sn9, "SN9", false, &mas_qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc); - -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_node mas_qhm_a1noc_cfg = { + .name = "mas_qhm_a1noc_cfg", + .id = SC8180X_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_A1NOC } +}; + +static struct qcom_icc_node mas_xm_ufs_card = { + .name = "mas_xm_ufs_card", + .id = SC8180X_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_ufs_g4 = { + .name = "mas_xm_ufs_g4", + .id = SC8180X_MASTER_UFS_GEN4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_ufs_mem = { + .name = "mas_xm_ufs_mem", + .id = SC8180X_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_0 = { + .name = "mas_xm_usb3_0", + .id = SC8180X_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_1 = { + .name = "mas_xm_usb3_1", + .id = SC8180X_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_2 = { + .name = "mas_xm_usb3_2", + .id = SC8180X_MASTER_USB3_2, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_a2noc_cfg = { + .name = "mas_qhm_a2noc_cfg", + .id = SC8180X_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_A2NOC } +}; + +static struct qcom_icc_node mas_qhm_qdss_bam = { + .name = "mas_qhm_qdss_bam", + .id = SC8180X_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qspi = { + .name = "mas_qhm_qspi", + .id = SC8180X_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qspi1 = { + .name = "mas_qhm_qspi1", + .id = SC8180X_MASTER_QSPI_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup0 = { + .name = "mas_qhm_qup0", + .id = SC8180X_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup1 = { + .name = "mas_qhm_qup1", + .id = SC8180X_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup2 = { + .name = "mas_qhm_qup2", + .id = SC8180X_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_sensorss_ahb = { + .name = "mas_qhm_sensorss_ahb", + .id = SC8180X_MASTER_SENSORS_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_crypto = { + .name = "mas_qxm_crypto", + .id = SC8180X_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_ipa = { + .name = "mas_qxm_ipa", + .id = SC8180X_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_emac = { + .name = "mas_xm_emac", + .id = SC8180X_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_pcie3_0 = { + .name = "mas_xm_pcie3_0", + .id = SC8180X_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_1 = { + .name = "mas_xm_pcie3_1", + .id = SC8180X_MASTER_PCIE_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_2 = { + .name = "mas_xm_pcie3_2", + .id = SC8180X_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_3 = { + .name = "mas_xm_pcie3_3", + .id = SC8180X_MASTER_PCIE_3, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_qdss_etr = { + .name = "mas_xm_qdss_etr", + .id = SC8180X_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_sdc2 = { + .name = "mas_xm_sdc2", + .id = SC8180X_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_sdc4 = { + .name = "mas_xm_sdc4", + .id = SC8180X_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { + .name = "mas_qxm_camnoc_hf0_uncomp", + .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { + .name = "mas_qxm_camnoc_hf1_uncomp", + .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { + .name = "mas_qxm_camnoc_sf_uncomp", + .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qnm_npu = { + .name = "mas_qnm_npu", + .id = SC8180X_MASTER_NPU, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CDSP_MEM_NOC } +}; + +static struct qcom_icc_node mas_qnm_snoc = { + .name = "mas_qnm_snoc", + .id = SC8180X_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 56, + .links = { SC8180X_SLAVE_TLMM_SOUTH, + SC8180X_SLAVE_CDSP_CFG, + SC8180X_SLAVE_SPSS_CFG, + SC8180X_SLAVE_CAMERA_CFG, + SC8180X_SLAVE_SDCC_4, + SC8180X_SLAVE_AHB2PHY_CENTER, + SC8180X_SLAVE_SDCC_2, + SC8180X_SLAVE_PCIE_2_CFG, + SC8180X_SLAVE_CNOC_MNOC_CFG, + SC8180X_SLAVE_EMAC_CFG, + SC8180X_SLAVE_QSPI_0, + SC8180X_SLAVE_QSPI_1, + SC8180X_SLAVE_TLMM_EAST, + SC8180X_SLAVE_SNOC_CFG, + SC8180X_SLAVE_AHB2PHY_EAST, + SC8180X_SLAVE_GLM, + SC8180X_SLAVE_PDM, + SC8180X_SLAVE_PCIE_1_CFG, + SC8180X_SLAVE_A2NOC_CFG, + SC8180X_SLAVE_QDSS_CFG, + SC8180X_SLAVE_DISPLAY_CFG, + SC8180X_SLAVE_TCSR, + SC8180X_SLAVE_UFS_MEM_0_CFG, + SC8180X_SLAVE_CNOC_DDRSS, + SC8180X_SLAVE_PCIE_0_CFG, + SC8180X_SLAVE_QUP_1, + SC8180X_SLAVE_QUP_2, + SC8180X_SLAVE_NPU_CFG, + SC8180X_SLAVE_CRYPTO_0_CFG, + SC8180X_SLAVE_GRAPHICS_3D_CFG, + SC8180X_SLAVE_VENUS_CFG, + SC8180X_SLAVE_TSIF, + SC8180X_SLAVE_IPA_CFG, + SC8180X_SLAVE_CLK_CTL, + SC8180X_SLAVE_SECURITY, + SC8180X_SLAVE_AOP, + SC8180X_SLAVE_AHB2PHY_WEST, + SC8180X_SLAVE_AHB2PHY_SOUTH, + SC8180X_SLAVE_SERVICE_CNOC, + SC8180X_SLAVE_UFS_CARD_CFG, + SC8180X_SLAVE_USB3_1, + SC8180X_SLAVE_USB3_2, + SC8180X_SLAVE_PCIE_3_CFG, + SC8180X_SLAVE_RBCPR_CX_CFG, + SC8180X_SLAVE_TLMM_WEST, + SC8180X_SLAVE_A1NOC_CFG, + SC8180X_SLAVE_AOSS, + SC8180X_SLAVE_PRNG, + SC8180X_SLAVE_VSENSE_CTRL_CFG, + SC8180X_SLAVE_QUP_0, + SC8180X_SLAVE_USB3, + SC8180X_SLAVE_RBCPR_MMCX_CFG, + SC8180X_SLAVE_PIMEM_CFG, + SC8180X_SLAVE_UFS_MEM_1_CFG, + SC8180X_SLAVE_RBCPR_MX_CFG, + SC8180X_SLAVE_IMEM_CFG } +}; + +static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { + .name = "mas_qhm_cnoc_dc_noc", + .id = SC8180X_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC_CFG, + SC8180X_SLAVE_GEM_NOC_CFG } +}; + +static struct qcom_icc_node mas_acm_apps = { + .name = "mas_acm_apps", + .id = SC8180X_MASTER_AMPSS_M0, + .channels = 4, + .buswidth = 64, + .num_links = 3, + .links = { SC8180X_SLAVE_ECC, + SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_acm_gpu_tcu = { + .name = "mas_acm_gpu_tcu", + .id = SC8180X_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_acm_sys_tcu = { + .name = "mas_acm_sys_tcu", + .id = SC8180X_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qhm_gemnoc_cfg = { + .name = "mas_qhm_gemnoc_cfg", + .id = SC8180X_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, + SC8180X_SLAVE_SERVICE_GEM_NOC, + SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } +}; + +static struct qcom_icc_node mas_qnm_cmpnoc = { + .name = "mas_qnm_cmpnoc", + .id = SC8180X_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SC8180X_SLAVE_ECC, + SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_gpu = { + .name = "mas_qnm_gpu", + .id = SC8180X_MASTER_GRAPHICS_3D, + .channels = 4, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_mnoc_hf = { + .name = "mas_qnm_mnoc_hf", + .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qnm_mnoc_sf = { + .name = "mas_qnm_mnoc_sf", + .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_pcie = { + .name = "mas_qnm_pcie", + .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_snoc_gc = { + .name = "mas_qnm_snoc_gc", + .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qnm_snoc_sf = { + .name = "mas_qnm_snoc_sf", + .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qxm_ecc = { + .name = "mas_qxm_ecc", + .id = SC8180X_MASTER_ECC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_ipa_core_master = { + .name = "mas_ipa_core_master", + .id = SC8180X_MASTER_IPA_CORE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_IPA_CORE } +}; + +static struct qcom_icc_node mas_llcc_mc = { + .name = "mas_llcc_mc", + .id = SC8180X_MASTER_LLCC, + .channels = 8, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_EBI_CH0 } +}; + +static struct qcom_icc_node mas_qhm_mnoc_cfg = { + .name = "mas_qhm_mnoc_cfg", + .id = SC8180X_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_MNOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf0 = { + .name = "mas_qxm_camnoc_hf0", + .id = SC8180X_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf1 = { + .name = "mas_qxm_camnoc_hf1", + .id = SC8180X_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_sf = { + .name = "mas_qxm_camnoc_sf", + .id = SC8180X_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_mdp0 = { + .name = "mas_qxm_mdp0", + .id = SC8180X_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_mdp1 = { + .name = "mas_qxm_mdp1", + .id = SC8180X_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_rot = { + .name = "mas_qxm_rot", + .id = SC8180X_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus0 = { + .name = "mas_qxm_venus0", + .id = SC8180X_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus1 = { + .name = "mas_qxm_venus1", + .id = SC8180X_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus_arm9 = { + .name = "mas_qxm_venus_arm9", + .id = SC8180X_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qhm_snoc_cfg = { + .name = "mas_qhm_snoc_cfg", + .id = SC8180X_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_SNOC } +}; + +static struct qcom_icc_node mas_qnm_aggre1_noc = { + .name = "mas_qnm_aggre1_noc", + .id = SC8180X_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 32, + .num_links = 6, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, + SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qnm_aggre2_noc = { + .name = "mas_qnm_aggre2_noc", + .id = SC8180X_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 11, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, + SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_PCIE_3, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SLAVE_PCIE_2, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_PCIE_0, + SC8180X_SLAVE_PCIE_1, + SC8180X_SLAVE_TCU, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qnm_gemnoc = { + .name = "mas_qnm_gemnoc", + .id = SC8180X_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_TCU, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qxm_pimem = { + .name = "mas_qxm_pimem", + .id = SC8180X_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, + SC8180X_SLAVE_OCIMEM } +}; + +static struct qcom_icc_node mas_xm_gic = { + .name = "mas_xm_gic", + .id = SC8180X_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, + SC8180X_SLAVE_OCIMEM } +}; + +static struct qcom_icc_node mas_qup_core_0 = { + .name = "mas_qup_core_0", + .id = SC8180X_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_0 } +}; + +static struct qcom_icc_node mas_qup_core_1 = { + .name = "mas_qup_core_1", + .id = SC8180X_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_1 } +}; + +static struct qcom_icc_node mas_qup_core_2 = { + .name = "mas_qup_core_2", + .id = SC8180X_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_2 } +}; + +static struct qcom_icc_node slv_qns_a1noc_snoc = { + .name = "slv_qns_a1noc_snoc", + .id = SC8180X_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_MAS } +}; + +static struct qcom_icc_node slv_srvc_aggre1_noc = { + .name = "slv_srvc_aggre1_noc", + .id = SC8180X_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_a2noc_snoc = { + .name = "slv_qns_a2noc_snoc", + .id = SC8180X_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_MAS } +}; + +static struct qcom_icc_node slv_qns_pcie_mem_noc = { + .name = "slv_qns_pcie_mem_noc", + .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } +}; + +static struct qcom_icc_node slv_srvc_aggre2_noc = { + .name = "slv_srvc_aggre2_noc", + .id = SC8180X_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_camnoc_uncomp = { + .name = "slv_qns_camnoc_uncomp", + .id = SC8180X_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32 +}; + +static struct qcom_icc_node slv_qns_cdsp_mem_noc = { + .name = "slv_qns_cdsp_mem_noc", + .id = SC8180X_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_COMPUTE_NOC } +}; + +static struct qcom_icc_node slv_qhs_a1_noc_cfg = { + .name = "slv_qhs_a1_noc_cfg", + .id = SC8180X_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_A1NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_a2_noc_cfg = { + .name = "slv_qhs_a2_noc_cfg", + .id = SC8180X_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_A2NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { + .name = "slv_qhs_ahb2phy_refgen_center", + .id = SC8180X_SLAVE_AHB2PHY_CENTER, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { + .name = "slv_qhs_ahb2phy_refgen_east", + .id = SC8180X_SLAVE_AHB2PHY_EAST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { + .name = "slv_qhs_ahb2phy_refgen_west", + .id = SC8180X_SLAVE_AHB2PHY_WEST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_south = { + .name = "slv_qhs_ahb2phy_south", + .id = SC8180X_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_aop = { + .name = "slv_qhs_aop", + .id = SC8180X_SLAVE_AOP, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_aoss = { + .name = "slv_qhs_aoss", + .id = SC8180X_SLAVE_AOSS, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_camera_cfg = { + .name = "slv_qhs_camera_cfg", + .id = SC8180X_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_clk_ctl = { + .name = "slv_qhs_clk_ctl", + .id = SC8180X_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_compute_dsp = { + .name = "slv_qhs_compute_dsp", + .id = SC8180X_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_cx = { + .name = "slv_qhs_cpr_cx", + .id = SC8180X_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_mmcx = { + .name = "slv_qhs_cpr_mmcx", + .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_mx = { + .name = "slv_qhs_cpr_mx", + .id = SC8180X_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_crypto0_cfg = { + .name = "slv_qhs_crypto0_cfg", + .id = SC8180X_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ddrss_cfg = { + .name = "slv_qhs_ddrss_cfg", + .id = SC8180X_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_CNOC_DC_NOC } +}; + +static struct qcom_icc_node slv_qhs_display_cfg = { + .name = "slv_qhs_display_cfg", + .id = SC8180X_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_emac_cfg = { + .name = "slv_qhs_emac_cfg", + .id = SC8180X_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_glm = { + .name = "slv_qhs_glm", + .id = SC8180X_SLAVE_GLM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_gpuss_cfg = { + .name = "slv_qhs_gpuss_cfg", + .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qhs_imem_cfg = { + .name = "slv_qhs_imem_cfg", + .id = SC8180X_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ipa = { + .name = "slv_qhs_ipa", + .id = SC8180X_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_mnoc_cfg = { + .name = "slv_qhs_mnoc_cfg", + .id = SC8180X_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_CNOC_MNOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_npu_cfg = { + .name = "slv_qhs_npu_cfg", + .id = SC8180X_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie0_cfg = { + .name = "slv_qhs_pcie0_cfg", + .id = SC8180X_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie1_cfg = { + .name = "slv_qhs_pcie1_cfg", + .id = SC8180X_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie2_cfg = { + .name = "slv_qhs_pcie2_cfg", + .id = SC8180X_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie3_cfg = { + .name = "slv_qhs_pcie3_cfg", + .id = SC8180X_SLAVE_PCIE_3_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pdm = { + .name = "slv_qhs_pdm", + .id = SC8180X_SLAVE_PDM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pimem_cfg = { + .name = "slv_qhs_pimem_cfg", + .id = SC8180X_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_prng = { + .name = "slv_qhs_prng", + .id = SC8180X_SLAVE_PRNG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qdss_cfg = { + .name = "slv_qhs_qdss_cfg", + .id = SC8180X_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qspi_0 = { + .name = "slv_qhs_qspi_0", + .id = SC8180X_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qspi_1 = { + .name = "slv_qhs_qspi_1", + .id = SC8180X_SLAVE_QSPI_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_east0 = { + .name = "slv_qhs_qupv3_east0", + .id = SC8180X_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_east1 = { + .name = "slv_qhs_qupv3_east1", + .id = SC8180X_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_west = { + .name = "slv_qhs_qupv3_west", + .id = SC8180X_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_sdc2 = { + .name = "slv_qhs_sdc2", + .id = SC8180X_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_sdc4 = { + .name = "slv_qhs_sdc4", + .id = SC8180X_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_security = { + .name = "slv_qhs_security", + .id = SC8180X_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_snoc_cfg = { + .name = "slv_qhs_snoc_cfg", + .id = SC8180X_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_spss_cfg = { + .name = "slv_qhs_spss_cfg", + .id = SC8180X_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tcsr = { + .name = "slv_qhs_tcsr", + .id = SC8180X_SLAVE_TCSR, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_east = { + .name = "slv_qhs_tlmm_east", + .id = SC8180X_SLAVE_TLMM_EAST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_south = { + .name = "slv_qhs_tlmm_south", + .id = SC8180X_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_west = { + .name = "slv_qhs_tlmm_west", + .id = SC8180X_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tsif = { + .name = "slv_qhs_tsif", + .id = SC8180X_SLAVE_TSIF, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_card_cfg = { + .name = "slv_qhs_ufs_card_cfg", + .id = SC8180X_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { + .name = "slv_qhs_ufs_mem0_cfg", + .id = SC8180X_SLAVE_UFS_MEM_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { + .name = "slv_qhs_ufs_mem1_cfg", + .id = SC8180X_SLAVE_UFS_MEM_1_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_0 = { + .name = "slv_qhs_usb3_0", + .id = SC8180X_SLAVE_USB3, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_1 = { + .name = "slv_qhs_usb3_1", + .id = SC8180X_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_2 = { + .name = "slv_qhs_usb3_2", + .id = SC8180X_SLAVE_USB3_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_venus_cfg = { + .name = "slv_qhs_venus_cfg", + .id = SC8180X_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { + .name = "slv_qhs_vsense_ctrl_cfg", + .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_srvc_cnoc = { + .name = "slv_srvc_cnoc", + .id = SC8180X_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_gemnoc = { + .name = "slv_qhs_gemnoc", + .id = SC8180X_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_llcc = { + .name = "slv_qhs_llcc", + .id = SC8180X_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { + .name = "slv_qhs_mdsp_ms_mpu_cfg", + .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_ecc = { + .name = "slv_qns_ecc", + .id = SC8180X_SLAVE_ECC, + .channels = 1, + .buswidth = 32 +}; + +static struct qcom_icc_node slv_qns_gem_noc_snoc = { + .name = "slv_qns_gem_noc_snoc", + .id = SC8180X_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node slv_qns_llcc = { + .name = "slv_qns_llcc", + .id = SC8180X_SLAVE_LLCC, + .channels = 8, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_MASTER_LLCC } +}; + +static struct qcom_icc_node slv_srvc_gemnoc = { + .name = "slv_srvc_gemnoc", + .id = SC8180X_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_srvc_gemnoc1 = { + .name = "slv_srvc_gemnoc1", + .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_ipa_core_slave = { + .name = "slv_ipa_core_slave", + .id = SC8180X_SLAVE_IPA_CORE, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_ebi = { + .name = "slv_ebi", + .id = SC8180X_SLAVE_EBI_CH0, + .channels = 8, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns2_mem_noc = { + .name = "slv_qns2_mem_noc", + .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node slv_qns_mem_noc_hf = { + .name = "slv_qns_mem_noc_hf", + .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node slv_srvc_mnoc = { + .name = "slv_srvc_mnoc", + .id = SC8180X_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_apss = { + .name = "slv_qhs_apss", + .id = SC8180X_SLAVE_APPSS, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qns_cnoc = { + .name = "slv_qns_cnoc", + .id = SC8180X_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SNOC_CNOC_MAS } +}; + +static struct qcom_icc_node slv_qns_gemnoc_gc = { + .name = "slv_qns_gemnoc_gc", + .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } +}; + +static struct qcom_icc_node slv_qns_gemnoc_sf = { + .name = "slv_qns_gemnoc_sf", + .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node slv_qxs_imem = { + .name = "slv_qxs_imem", + .id = SC8180X_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qxs_pimem = { + .name = "slv_qxs_pimem", + .id = SC8180X_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = SC8180X_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_xs_pcie_0 = { + .name = "slv_xs_pcie_0", + .id = SC8180X_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_1 = { + .name = "slv_xs_pcie_1", + .id = SC8180X_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_2 = { + .name = "slv_xs_pcie_2", + .id = SC8180X_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_3 = { + .name = "slv_xs_pcie_3", + .id = SC8180X_SLAVE_PCIE_3, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_qdss_stm = { + .name = "slv_xs_qdss_stm", + .id = SC8180X_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_xs_sys_tcu_cfg = { + .name = "slv_xs_sys_tcu_cfg", + .id = SC8180X_SLAVE_TCU, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qup_core_0 = { + .name = "slv_qup_core_0", + .id = SC8180X_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qup_core_1 = { + .name = "slv_qup_core_1", + .id = SC8180X_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qup_core_2 = { + .name = "slv_qup_core_2", + .id = SC8180X_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &slv_ebi } +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &slv_ebi } +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &slv_qns_llcc } +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &slv_qns_mem_noc_hf } +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .num_nodes = 1, + .nodes = { &slv_qns_cdsp_mem_noc } +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &mas_qxm_crypto } +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 57, + .nodes = { &mas_qnm_snoc, + &slv_qhs_a1_noc_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_qhs_aop, + &slv_qhs_aoss, + &slv_qhs_camera_cfg, + &slv_qhs_clk_ctl, + &slv_qhs_compute_dsp, + &slv_qhs_cpr_cx, + &slv_qhs_cpr_mmcx, + &slv_qhs_cpr_mx, + &slv_qhs_crypto0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_glm, + &slv_qhs_gpuss_cfg, + &slv_qhs_imem_cfg, + &slv_qhs_ipa, + &slv_qhs_mnoc_cfg, + &slv_qhs_npu_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_pcie1_cfg, + &slv_qhs_pcie2_cfg, + &slv_qhs_pcie3_cfg, + &slv_qhs_pdm, + &slv_qhs_pimem_cfg, + &slv_qhs_prng, + &slv_qhs_qdss_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_qupv3_west, + &slv_qhs_sdc2, + &slv_qhs_sdc4, + &slv_qhs_security, + &slv_qhs_snoc_cfg, + &slv_qhs_spss_cfg, + &slv_qhs_tcsr, + &slv_qhs_tlmm_east, + &slv_qhs_tlmm_south, + &slv_qhs_tlmm_west, + &slv_qhs_tsif, + &slv_qhs_ufs_card_cfg, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_usb3_0, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_venus_cfg, + &slv_qhs_vsense_ctrl_cfg, + &slv_srvc_cnoc } +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 7, + .nodes = { &mas_qxm_camnoc_hf0_uncomp, + &mas_qxm_camnoc_hf1_uncomp, + &mas_qxm_camnoc_sf_uncomp, + &mas_qxm_camnoc_hf0, + &mas_qxm_camnoc_hf1, + &mas_qxm_mdp0, + &mas_qxm_mdp1 } +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .num_nodes = 3, + .nodes = { &mas_qup_core_0, + &mas_qup_core_1, + &mas_qup_core_2 } +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &slv_qns_gem_noc_snoc } +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .num_nodes = 6, + .nodes = { &mas_qxm_camnoc_sf, + &mas_qxm_rot, + &mas_qxm_venus0, + &mas_qxm_venus1, + &mas_qxm_venus_arm9, + &slv_qns2_mem_noc } +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = true, + .num_nodes = 1, + .nodes = { &mas_acm_apps } +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .nodes = { &slv_qns_gemnoc_sf } +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .nodes = { &slv_qxs_imem } +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = true, + .nodes = { &slv_qns_gemnoc_gc } +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .nodes = { &mas_qnm_npu } +}; + +static struct qcom_icc_bcm bcm_ip0 = { + .name = "IP0", + .nodes = { &slv_ipa_core_slave } +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = true, + .nodes = { &slv_srvc_aggre1_noc, + &slv_qns_cnoc } +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .nodes = { &slv_qxs_pimem } +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .num_nodes = 4, + .nodes = { &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_pcie_2, + &slv_xs_pcie_3 } +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 1, + .nodes = { &mas_qnm_aggre1_noc } +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .num_nodes = 1, + .nodes = { &mas_qnm_aggre2_noc } +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .num_nodes = 1, + .nodes = { &slv_qns_pcie_mem_noc } +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = true, + .num_nodes = 1, + .nodes = { &mas_qnm_gemnoc } +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn3, &bcm_ce0, - &bcm_qup0, }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_sn14, &bcm_ce0, - &bcm_qup0, }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, &bcm_acv, }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, @@ -249,7 +1631,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn15, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, [MASTER_UFS_CARD] = &mas_xm_ufs_card, [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, @@ -261,7 +1643,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, [MASTER_QSPI_0] = &mas_qhm_qspi, @@ -285,19 +1667,19 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &mas_qnm_npu, [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [SNOC_CNOC_MAS] = &mas_qnm_snoc, [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, @@ -357,13 +1739,13 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, [SLAVE_LLCC_CFG] = &slv_qhs_llcc, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_AMPSS_M0] = &mas_acm_apps, [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, [MASTER_SYS_TCU] = &mas_acm_sys_tcu, @@ -384,17 +1766,17 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &mas_ipa_core_master, [SLAVE_IPA_CORE] = &slv_ipa_core_slave, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &mas_llcc_mc, [SLAVE_EBI_CH0] = &slv_ebi, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, @@ -410,7 +1792,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, @@ -503,97 +1885,25 @@ static const struct qcom_icc_desc sc8180x_system_noc = { .num_bcms = ARRAY_SIZE(system_noc_bcms), }; -static int qnoc_probe(struct platform_device *pdev) -{ - const struct qcom_icc_desc *desc; - struct icc_onecell_data *data; - struct icc_provider *provider; - struct qcom_icc_node **qnodes; - struct qcom_icc_provider *qp; - struct icc_node *node; - size_t num_nodes, i; - int ret; - - desc = device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; - - qnodes = desc->nodes; - num_nodes = desc->num_nodes; - - qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); - if (!qp) - return -ENOMEM; - - data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); - if (!data) - return -ENOMEM; - - provider = &qp->provider; - provider->dev = &pdev->dev; - provider->set = qcom_icc_set; - provider->pre_aggregate = qcom_icc_pre_aggregate; - provider->aggregate = qcom_icc_aggregate; - provider->xlate = of_icc_xlate_onecell; - INIT_LIST_HEAD(&provider->nodes); - provider->data = data; - - qp->dev = &pdev->dev; - qp->bcms = desc->bcms; - qp->num_bcms = desc->num_bcms; - - qp->voter = of_bcm_voter_get(qp->dev, NULL); - if (IS_ERR(qp->voter)) - return PTR_ERR(qp->voter); - - ret = icc_provider_add(provider); - if (ret) { - dev_err(&pdev->dev, "error adding interconnect provider\n"); - return ret; - } - - for (i = 0; i < qp->num_bcms; i++) - qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); - - for (i = 0; i < num_nodes; i++) { - size_t j; - - if (!qnodes[i]) - continue; - - node = icc_node_create(qnodes[i]->id); - if (IS_ERR(node)) { - ret = PTR_ERR(node); - goto err; - } - - node->name = qnodes[i]->name; - node->data = qnodes[i]; - icc_node_add(node, provider); - - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - - data->nodes[i] = node; - } - data->num_nodes = num_nodes; - - platform_set_drvdata(pdev, qp); - - return 0; -err: - icc_nodes_remove(provider); - icc_provider_del(provider); - return ret; -} - -static int qnoc_remove(struct platform_device *pdev) -{ - struct qcom_icc_provider *qp = platform_get_drvdata(pdev); - - icc_nodes_remove(&qp->provider); - return icc_provider_del(&qp->provider); -} +static struct qcom_icc_bcm * const qup_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node *qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &mas_qup_core_0, + [MASTER_QUP_CORE_1] = &mas_qup_core_1, + [MASTER_QUP_CORE_2] = &mas_qup_core_2, + [SLAVE_QUP_CORE_0] = &slv_qup_core_0, + [SLAVE_QUP_CORE_1] = &slv_qup_core_1, + [SLAVE_QUP_CORE_2] = &slv_qup_core_2, +}; + +static const struct qcom_icc_desc sc8180x_qup_virt = { + .nodes = qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qup_virt_nodes), + .bcms = qup_virt_bcms, + .num_bcms = ARRAY_SIZE(qup_virt_bcms), +}; static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, @@ -606,14 +1916,15 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt }, { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, + { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt }, { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc }, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { - .probe = qnoc_probe, - .remove = qnoc_remove, + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8180x", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h index e70cf7032f80..2eafd35543c7 100644 --- a/drivers/interconnect/qcom/sc8180x.h +++ b/drivers/interconnect/qcom/sc8180x.h @@ -171,4 +171,11 @@ #define SC8180X_MASTER_OSM_L3_APPS 161 #define SC8180X_SLAVE_OSM_L3 162 +#define SC8180X_MASTER_QUP_CORE_0 163 +#define SC8180X_MASTER_QUP_CORE_1 164 +#define SC8180X_MASTER_QUP_CORE_2 165 +#define SC8180X_SLAVE_QUP_CORE_0 166 +#define SC8180X_SLAVE_QUP_CORE_1 167 +#define SC8180X_SLAVE_QUP_CORE_2 168 + #endif diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c new file mode 100644 index 000000000000..507fe5f89791 --- /dev/null +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -0,0 +1,2438 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,sc8280xp.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sc8280xp.h" + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SC8280XP_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SC8280XP_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SC8280XP_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg = { + .name = "qnm_a1noc_cfg", + .id = SC8280XP_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .links = { SC8280XP_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SC8280XP_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_1 = { + .name = "xm_emac_1", + .id = SC8280XP_MASTER_EMAC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SC8280XP_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SC8280XP_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SC8280XP_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SC8280XP_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_mp = { + .name = "xm_usb3_mp", + .id = SC8280XP_MASTER_USB3_MP, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb4_host0 = { + .name = "xm_usb4_host0", + .id = SC8280XP_MASTER_USB4_0, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb4_host1 = { + .name = "xm_usb4_host1", + .id = SC8280XP_MASTER_USB4_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SC8280XP_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SC8280XP_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg = { + .name = "qnm_a2noc_cfg", + .id = SC8280XP_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SC8280XP_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_sensorss_q6 = { + .name = "qxm_sensorss_q6", + .id = SC8280XP_MASTER_SENSORS_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .id = SC8280XP_MASTER_SP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_0 = { + .name = "xm_emac_0", + .id = SC8280XP_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SC8280XP_MASTER_PCIE_0, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SC8280XP_MASTER_PCIE_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_2a = { + .name = "xm_pcie3_2a", + .id = SC8280XP_MASTER_PCIE_2A, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_2b = { + .name = "xm_pcie3_2b", + .id = SC8280XP_MASTER_PCIE_2B, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_3a = { + .name = "xm_pcie3_3a", + .id = SC8280XP_MASTER_PCIE_3A, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_3b = { + .name = "xm_pcie3_3b", + .id = SC8280XP_MASTER_PCIE_3B, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_4 = { + .name = "xm_pcie3_4", + .id = SC8280XP_MASTER_PCIE_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SC8280XP_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SC8280XP_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SC8280XP_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node ipa_core_master = { + .name = "ipa_core_master", + .id = SC8280XP_MASTER_IPA_CORE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_IPA_CORE }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SC8280XP_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SC8280XP_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SC8280XP_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SC8280XP_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 76, + .links = { SC8280XP_SLAVE_AHB2PHY_0, + SC8280XP_SLAVE_AHB2PHY_1, + SC8280XP_SLAVE_AHB2PHY_2, + SC8280XP_SLAVE_AOSS, + SC8280XP_SLAVE_APPSS, + SC8280XP_SLAVE_CAMERA_CFG, + SC8280XP_SLAVE_CLK_CTL, + SC8280XP_SLAVE_CDSP_CFG, + SC8280XP_SLAVE_CDSP1_CFG, + SC8280XP_SLAVE_RBCPR_CX_CFG, + SC8280XP_SLAVE_RBCPR_MMCX_CFG, + SC8280XP_SLAVE_RBCPR_MX_CFG, + SC8280XP_SLAVE_CPR_NSPCX, + SC8280XP_SLAVE_CRYPTO_0_CFG, + SC8280XP_SLAVE_CX_RDPM, + SC8280XP_SLAVE_DCC_CFG, + SC8280XP_SLAVE_DISPLAY_CFG, + SC8280XP_SLAVE_DISPLAY1_CFG, + SC8280XP_SLAVE_EMAC_CFG, + SC8280XP_SLAVE_EMAC1_CFG, + SC8280XP_SLAVE_GFX3D_CFG, + SC8280XP_SLAVE_HWKM, + SC8280XP_SLAVE_IMEM_CFG, + SC8280XP_SLAVE_IPA_CFG, + SC8280XP_SLAVE_IPC_ROUTER_CFG, + SC8280XP_SLAVE_LPASS, + SC8280XP_SLAVE_MX_RDPM, + SC8280XP_SLAVE_MXC_RDPM, + SC8280XP_SLAVE_PCIE_0_CFG, + SC8280XP_SLAVE_PCIE_1_CFG, + SC8280XP_SLAVE_PCIE_2A_CFG, + SC8280XP_SLAVE_PCIE_2B_CFG, + SC8280XP_SLAVE_PCIE_3A_CFG, + SC8280XP_SLAVE_PCIE_3B_CFG, + SC8280XP_SLAVE_PCIE_4_CFG, + SC8280XP_SLAVE_PCIE_RSC_CFG, + SC8280XP_SLAVE_PDM, + SC8280XP_SLAVE_PIMEM_CFG, + SC8280XP_SLAVE_PKA_WRAPPER_CFG, + SC8280XP_SLAVE_PMU_WRAPPER_CFG, + SC8280XP_SLAVE_QDSS_CFG, + SC8280XP_SLAVE_QSPI_0, + SC8280XP_SLAVE_QUP_0, + SC8280XP_SLAVE_QUP_1, + SC8280XP_SLAVE_QUP_2, + SC8280XP_SLAVE_SDCC_2, + SC8280XP_SLAVE_SDCC_4, + SC8280XP_SLAVE_SECURITY, + SC8280XP_SLAVE_SMMUV3_CFG, + SC8280XP_SLAVE_SMSS_CFG, + SC8280XP_SLAVE_SPSS_CFG, + SC8280XP_SLAVE_TCSR, + SC8280XP_SLAVE_TLMM, + SC8280XP_SLAVE_UFS_CARD_CFG, + SC8280XP_SLAVE_UFS_MEM_CFG, + SC8280XP_SLAVE_USB3_0, + SC8280XP_SLAVE_USB3_1, + SC8280XP_SLAVE_USB3_MP, + SC8280XP_SLAVE_USB4_0, + SC8280XP_SLAVE_USB4_1, + SC8280XP_SLAVE_VENUS_CFG, + SC8280XP_SLAVE_VSENSE_CTRL_CFG, + SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, + SC8280XP_SLAVE_A1NOC_CFG, + SC8280XP_SLAVE_A2NOC_CFG, + SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, + SC8280XP_SLAVE_DDRSS_CFG, + SC8280XP_SLAVE_CNOC_MNOC_CFG, + SC8280XP_SLAVE_SNOC_CFG, + SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, + SC8280XP_SLAVE_IMEM, + SC8280XP_SLAVE_PIMEM, + SC8280XP_SLAVE_SERVICE_CNOC, + SC8280XP_SLAVE_QDSS_STM, + SC8280XP_SLAVE_SMSS, + SC8280XP_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SC8280XP_SLAVE_PCIE_0, + SC8280XP_SLAVE_PCIE_1, + SC8280XP_SLAVE_PCIE_2A, + SC8280XP_SLAVE_PCIE_2B, + SC8280XP_SLAVE_PCIE_3A, + SC8280XP_SLAVE_PCIE_3B, + SC8280XP_SLAVE_PCIE_4 + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .id = SC8280XP_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC8280XP_SLAVE_LLCC_CFG, + SC8280XP_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SC8280XP_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_pcie_tcu = { + .name = "alm_pcie_tcu", + .id = SC8280XP_MASTER_PCIE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SC8280XP_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SC8280XP_MASTER_APPSS_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC, + SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc0 = { + .name = "qnm_cmpnoc0", + .id = SC8280XP_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc1 = { + .name = "qnm_cmpnoc1", + .id = SC8280XP_MASTER_COMPUTE_NOC_1, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SC8280XP_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, + SC8280XP_SLAVE_SERVICE_GEM_NOC_2, + SC8280XP_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SC8280XP_MASTER_GFX3D, + .channels = 4, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_LLCC, + SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, + SC8280XP_SLAVE_LLCC, + SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 6, + .links = { SC8280XP_SLAVE_LPASS_CORE_CFG, + SC8280XP_SLAVE_LPASS_LPI_CFG, + SC8280XP_SLAVE_LPASS_MPU_CFG, + SC8280XP_SLAVE_LPASS_TOP_CFG, + SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, + SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .id = SC8280XP_MASTER_LPASS_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 4, + .links = { SC8280XP_SLAVE_LPASS_TOP_CFG, + SC8280XP_SLAVE_LPASS_SNOC, + SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, + SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SC8280XP_MASTER_LLCC, + .channels = 8, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SC8280XP_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_0 = { + .name = "qnm_mdp0_0", + .id = SC8280XP_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_1 = { + .name = "qnm_mdp0_1", + .id = SC8280XP_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_0 = { + .name = "qnm_mdp1_0", + .id = SC8280XP_MASTER_MDP_CORE1_0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_1 = { + .name = "qnm_mdp1_1", + .id = SC8280XP_MASTER_MDP_CORE1_1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .id = SC8280XP_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_rot_0 = { + .name = "qnm_rot_0", + .id = SC8280XP_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_rot_1 = { + .name = "qnm_rot_1", + .id = SC8280XP_MASTER_ROTATOR_1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SC8280XP_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SC8280XP_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SC8280XP_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_icp = { + .name = "qxm_camnoc_icp", + .id = SC8280XP_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SC8280XP_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = SC8280XP_MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = SC8280XP_MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_CDSP_MEM_NOC, + SC8280XP_SLAVE_NSP_XFR + }, +}; + +static struct qcom_icc_node qhm_nspb_noc_config = { + .name = "qhm_nspb_noc_config", + .id = SC8280XP_MASTER_CDSPB_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, +}; + +static struct qcom_icc_node qxm_nspb = { + .name = "qxm_nspb", + .id = SC8280XP_MASTER_CDSP_PROC_B, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC, + SC8280XP_SLAVE_NSPB_XFR + }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SC8280XP_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SC8280XP_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre_usb_noc = { + .name = "qnm_aggre_usb_noc", + .id = SC8280XP_MASTER_USB_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_lpass_noc = { + .name = "qnm_lpass_noc", + .id = SC8280XP_MASTER_LPASS_ANOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = SC8280XP_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SC8280XP_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SC8280XP_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SC8280XP_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qns_aggre_usb_snoc = { + .name = "qns_aggre_usb_snoc", + .id = SC8280XP_SLAVE_USB_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_USB_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SC8280XP_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SC8280XP_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_gem_noc = { + .name = "qns_pcie_gem_noc", + .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SC8280XP_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ipa_core_slave = { + .name = "ipa_core_slave", + .id = SC8280XP_SLAVE_IPA_CORE, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SC8280XP_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SC8280XP_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SC8280XP_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SC8280XP_SLAVE_AHB2PHY_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SC8280XP_SLAVE_AHB2PHY_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SC8280XP_SLAVE_AHB2PHY_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SC8280XP_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SC8280XP_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SC8280XP_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SC8280XP_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute0_cfg = { + .name = "qhs_compute0_cfg", + .id = SC8280XP_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_CDSP_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_compute1_cfg = { + .name = "qhs_compute1_cfg", + .id = SC8280XP_SLAVE_CDSP1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_CDSPB_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SC8280XP_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SC8280XP_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_nspcx = { + .name = "qhs_cpr_nspcx", + .id = SC8280XP_SLAVE_CPR_NSPCX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SC8280XP_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SC8280XP_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SC8280XP_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display0_cfg = { + .name = "qhs_display0_cfg", + .id = SC8280XP_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display1_cfg = { + .name = "qhs_display1_cfg", + .id = SC8280XP_SLAVE_DISPLAY1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac0_cfg = { + .name = "qhs_emac0_cfg", + .id = SC8280XP_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac1_cfg = { + .name = "qhs_emac1_cfg", + .id = SC8280XP_SLAVE_EMAC1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SC8280XP_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .id = SC8280XP_SLAVE_HWKM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SC8280XP_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SC8280XP_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SC8280XP_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SC8280XP_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SC8280XP_SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mxc_rdpm = { + .name = "qhs_mxc_rdpm", + .id = SC8280XP_SLAVE_MXC_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SC8280XP_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SC8280XP_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie2a_cfg = { + .name = "qhs_pcie2a_cfg", + .id = SC8280XP_SLAVE_PCIE_2A_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie2b_cfg = { + .name = "qhs_pcie2b_cfg", + .id = SC8280XP_SLAVE_PCIE_2B_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie3a_cfg = { + .name = "qhs_pcie3a_cfg", + .id = SC8280XP_SLAVE_PCIE_3A_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie3b_cfg = { + .name = "qhs_pcie3b_cfg", + .id = SC8280XP_SLAVE_PCIE_3B_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie4_cfg = { + .name = "qhs_pcie4_cfg", + .id = SC8280XP_SLAVE_PCIE_4_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_rsc_cfg = { + .name = "qhs_pcie_rsc_cfg", + .id = SC8280XP_SLAVE_PCIE_RSC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SC8280XP_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SC8280XP_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pka_wrapper_cfg = { + .name = "qhs_pka_wrapper_cfg", + .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg = { + .name = "qhs_pmu_wrapper_cfg", + .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SC8280XP_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SC8280XP_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SC8280XP_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SC8280XP_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SC8280XP_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SC8280XP_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SC8280XP_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SC8280XP_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_smmuv3_cfg = { + .name = "qhs_smmuv3_cfg", + .id = SC8280XP_SLAVE_SMMUV3_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_smss_cfg = { + .name = "qhs_smss_cfg", + .id = SC8280XP_SLAVE_SMSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SC8280XP_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SC8280XP_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SC8280XP_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SC8280XP_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SC8280XP_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SC8280XP_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SC8280XP_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_mp = { + .name = "qhs_usb3_mp", + .id = SC8280XP_SLAVE_USB3_MP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb4_host_0 = { + .name = "qhs_usb4_host_0", + .id = SC8280XP_SLAVE_USB4_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb4_host_1 = { + .name = "qhs_usb4_host_1", + .id = SC8280XP_SLAVE_USB4_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SC8280XP_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { + .name = "qhs_vsense_ctrl_r_cfg", + .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a1_noc_cfg = { + .name = "qns_a1_noc_cfg", + .id = SC8280XP_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qns_a2_noc_cfg = { + .name = "qns_a2_noc_cfg", + .id = SC8280XP_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { + .name = "qns_anoc_pcie_bridge_cfg", + .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SC8280XP_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .id = SC8280XP_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SC8280XP_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { + .name = "qns_snoc_sf_bridge_cfg", + .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SC8280XP_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SC8280XP_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SC8280XP_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SC8280XP_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SC8280XP_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_2a = { + .name = "xs_pcie_2a", + .id = SC8280XP_SLAVE_PCIE_2A, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_2b = { + .name = "xs_pcie_2b", + .id = SC8280XP_SLAVE_PCIE_2B, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_3a = { + .name = "xs_pcie_3a", + .id = SC8280XP_SLAVE_PCIE_3A, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_3b = { + .name = "xs_pcie_3b", + .id = SC8280XP_SLAVE_PCIE_3B, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_4 = { + .name = "xs_pcie_4", + .id = SC8280XP_SLAVE_PCIE_4, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SC8280XP_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_smss = { + .name = "xs_smss", + .id = SC8280XP_SLAVE_SMSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SC8280XP_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SC8280XP_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SC8280XP_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8280XP_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SC8280XP_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SC8280XP_SLAVE_LLCC, + .channels = 8, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SC8280XP_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SC8280XP_SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SC8280XP_SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SC8280XP_SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SC8280XP_SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_sysnoc = { + .name = "qns_sysnoc", + .id = SC8280XP_SLAVE_LPASS_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_LPASS_ANOC }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SC8280XP_SLAVE_EBI1, + .channels = 8, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SC8280XP_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SC8280XP_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qxs_nsp_xfr = { + .name = "qxs_nsp_xfr", + .id = SC8280XP_SLAVE_NSP_XFR, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SC8280XP_SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nspb_gemnoc = { + .name = "qns_nspb_gemnoc", + .id = SC8280XP_SLAVE_CDSPB_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8280XP_MASTER_COMPUTE_NOC_1 }, +}; + +static struct qcom_icc_node qxs_nspb_xfr = { + .name = "qxs_nspb_xfr", + .id = SC8280XP_SLAVE_NSPB_XFR, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node service_nspb_noc = { + .name = "service_nspb_noc", + .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SC8280XP_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 9, + .nodes = { &qnm_gemnoc_cnoc, + &qnm_gemnoc_pcie, + &xs_pcie_0, + &xs_pcie_1, + &xs_pcie_2a, + &xs_pcie_2b, + &xs_pcie_3a, + &xs_pcie_3b, + &xs_pcie_4 + }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 67, + .nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_ahb2phy2, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute0_cfg, + &qhs_compute1_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_cpr_nspcx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display0_cfg, + &qhs_display1_cfg, + &qhs_emac0_cfg, + &qhs_emac1_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mx_rdpm, + &qhs_mxc_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie2a_cfg, + &qhs_pcie2b_cfg, + &qhs_pcie3a_cfg, + &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, + &qhs_pcie_rsc_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_smmuv3_cfg, + &qhs_smss_cfg, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_usb3_mp, + &qhs_usb4_host_0, + &qhs_usb4_host_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_vsense_ctrl_r_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_anoc_pcie_bridge_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qns_snoc_sf_bridge_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .num_nodes = 4, + .nodes = { &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2 + }, +}; + +static struct qcom_icc_bcm bcm_cn3 = { + .name = "CN3", + .num_nodes = 3, + .nodes = { &qxs_imem, + &xs_smss, + &xs_sys_tcu_cfg + }, +}; + +static struct qcom_icc_bcm bcm_ip0 = { + .name = "IP0", + .num_nodes = 1, + .nodes = { &ipa_core_slave }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 5, + .nodes = { &qnm_camnoc_hf, + &qnm_mdp0_0, + &qnm_mdp0_1, + &qnm_mdp1_0, + &qns_mem_noc_hf + }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 8, + .nodes = { &qnm_rot_0, + &qnm_rot_1, + &qnm_video0, + &qnm_video1, + &qnm_video_cvp, + &qxm_camnoc_icp, + &qxm_camnoc_sf, + &qns_mem_noc_sf + }, +}; + +static struct qcom_icc_bcm bcm_nsa0 = { + .name = "NSA0", + .num_nodes = 2, + .nodes = { &qns_nsp_gemnoc, + &qxs_nsp_xfr + }, +}; + +static struct qcom_icc_bcm bcm_nsa1 = { + .name = "NSA1", + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_nsb0 = { + .name = "NSB0", + .num_nodes = 2, + .nodes = { &qns_nspb_gemnoc, + &qxs_nspb_xfr + }, +}; + +static struct qcom_icc_bcm bcm_nsb1 = { + .name = "NSB1", + .num_nodes = 1, + .nodes = { &qxm_nspb }, +}; + +static struct qcom_icc_bcm bcm_pci0 = { + .name = "PCI0", + .num_nodes = 1, + .nodes = { &qns_pcie_gem_noc }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 2, + .nodes = { &qns_a1noc_snoc, + &qnm_aggre1_noc + }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 2, + .nodes = { &qns_a2noc_snoc, + &qnm_aggre2_noc + }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .num_nodes = 2, + .nodes = { &qns_aggre_usb_snoc, + &qnm_aggre_usb_noc + }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 2, + .nodes = { &qns_sysnoc, + &qnm_lpass_noc + }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_sn3, + &bcm_sn5, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, + [MASTER_IPA] = &qxm_ipa, + [MASTER_EMAC_1] = &xm_emac_1, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3_0] = &xm_usb3_0, + [MASTER_USB3_1] = &xm_usb3_1, + [MASTER_USB3_MP] = &xm_usb3_mp, + [MASTER_USB4_0] = &xm_usb4_host0, + [MASTER_USB4_1] = &xm_usb4_host1, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, +}; + +static const struct qcom_icc_desc sc8280xp_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_pci0, + &bcm_sn4, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, + [MASTER_SP] = &qxm_sp, + [MASTER_EMAC] = &xm_emac_0, + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [MASTER_PCIE_2A] = &xm_pcie3_2a, + [MASTER_PCIE_2B] = &xm_pcie3_2b, + [MASTER_PCIE_3A] = &xm_pcie3_3a, + [MASTER_PCIE_3B] = &xm_pcie3_3b, + [MASTER_PCIE_4] = &xm_pcie3_4, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_UFS_CARD] = &xm_ufs_card, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static const struct qcom_icc_desc sc8280xp_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_ip0, + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_IPA_CORE] = &ipa_core_master, + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_IPA_CORE] = &ipa_core_slave, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc sc8280xp_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, + &bcm_cn2, + &bcm_cn3, + &bcm_sn2, + &bcm_sn10, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, + [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_DCC_CFG] = &qhs_dcc_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, + [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, + [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, + [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_HWKM] = &qhs_hwkm, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_LPASS] = &qhs_lpass_cfg, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, + [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, + [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, + [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, + [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, + [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, + [SLAVE_SMSS_CFG] = &qhs_smss_cfg, + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_USB3_1] = &qhs_usb3_1, + [SLAVE_USB3_MP] = &qhs_usb3_mp, + [SLAVE_USB4_0] = &qhs_usb4_host_0, + [SLAVE_USB4_1] = &qhs_usb4_host_1, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, + [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, + [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, + [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, + [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_PCIE_2A] = &xs_pcie_2a, + [SLAVE_PCIE_2B] = &xs_pcie_2b, + [SLAVE_PCIE_3A] = &xs_pcie_3a, + [SLAVE_PCIE_3B] = &xs_pcie_3b, + [SLAVE_PCIE_4] = &xs_pcie_4, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_SMSS] = &xs_smss, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sc8280xp_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const dc_noc_bcms[] = { +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, + [SLAVE_LLCC_CFG] = &qhs_llcc, + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, +}; + +static const struct qcom_icc_desc sc8280xp_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms = ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_PCIE_TCU] = &alm_pcie_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, + [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, + [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, + [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, + [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, +}; + +static const struct qcom_icc_desc sc8280xp_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { + &bcm_sn9, +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, + [SLAVE_LPASS_SNOC] = &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, +}; + +static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms = lpass_ag_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sc8280xp_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_MDP0] = &qnm_mdp0_0, + [MASTER_MDP1] = &qnm_mdp0_1, + [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, + [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, + [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, + [MASTER_ROTATOR] = &qnm_rot_0, + [MASTER_ROTATOR_1] = &qnm_rot_1, + [MASTER_VIDEO_P0] = &qnm_video0, + [MASTER_VIDEO_P1] = &qnm_video1, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sc8280xp_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nspa_noc_bcms[] = { + &bcm_nsa0, + &bcm_nsa1, +}; + +static struct qcom_icc_node * const nspa_noc_nodes[] = { + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, + [SLAVE_NSP_XFR] = &qxs_nsp_xfr, + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, +}; + +static const struct qcom_icc_desc sc8280xp_nspa_noc = { + .nodes = nspa_noc_nodes, + .num_nodes = ARRAY_SIZE(nspa_noc_nodes), + .bcms = nspa_noc_bcms, + .num_bcms = ARRAY_SIZE(nspa_noc_bcms), +}; + +static struct qcom_icc_bcm * const nspb_noc_bcms[] = { + &bcm_nsb0, + &bcm_nsb1, +}; + +static struct qcom_icc_node * const nspb_noc_nodes[] = { + [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, + [MASTER_CDSP_PROC_B] = &qxm_nspb, + [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, + [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, + [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, +}; + +static const struct qcom_icc_desc sc8280xp_nspb_noc = { + .nodes = nspb_noc_nodes, + .num_nodes = ARRAY_SIZE(nspb_noc_nodes), + .bcms = nspb_noc_bcms, + .num_bcms = ARRAY_SIZE(nspb_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_main_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn3, + &bcm_sn4, + &bcm_sn5, + &bcm_sn9, +}; + +static struct qcom_icc_node * const system_noc_main_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, + [MASTER_LPASS_ANOC] = &qnm_lpass_noc, + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, +}; + +static const struct qcom_icc_desc sc8280xp_system_noc_main = { + .nodes = system_noc_main_nodes, + .num_nodes = ARRAY_SIZE(system_noc_main_nodes), + .bcms = system_noc_main_bcms, + .num_bcms = ARRAY_SIZE(system_noc_main_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, + { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, + { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, + { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, + { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, + { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, + { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, + { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, + { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, + { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, + { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, + { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sc8280xp", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qcom/sc8280xp.h new file mode 100644 index 000000000000..74d8fa412d65 --- /dev/null +++ b/drivers/interconnect/qcom/sc8280xp.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H +#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H + +#define SC8280XP_MASTER_GPU_TCU 0 +#define SC8280XP_MASTER_PCIE_TCU 1 +#define SC8280XP_MASTER_SYS_TCU 2 +#define SC8280XP_MASTER_APPSS_PROC 3 +#define SC8280XP_MASTER_IPA_CORE 4 +#define SC8280XP_MASTER_LLCC 5 +#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6 +#define SC8280XP_MASTER_CDSP_NOC_CFG 7 +#define SC8280XP_MASTER_CDSPB_NOC_CFG 8 +#define SC8280XP_MASTER_QDSS_BAM 9 +#define SC8280XP_MASTER_QSPI_0 10 +#define SC8280XP_MASTER_QUP_0 11 +#define SC8280XP_MASTER_QUP_1 12 +#define SC8280XP_MASTER_QUP_2 13 +#define SC8280XP_MASTER_A1NOC_CFG 14 +#define SC8280XP_MASTER_A2NOC_CFG 15 +#define SC8280XP_MASTER_A1NOC_SNOC 16 +#define SC8280XP_MASTER_A2NOC_SNOC 17 +#define SC8280XP_MASTER_USB_NOC_SNOC 18 +#define SC8280XP_MASTER_CAMNOC_HF 19 +#define SC8280XP_MASTER_COMPUTE_NOC 20 +#define SC8280XP_MASTER_COMPUTE_NOC_1 21 +#define SC8280XP_MASTER_CNOC_DC_NOC 22 +#define SC8280XP_MASTER_GEM_NOC_CFG 23 +#define SC8280XP_MASTER_GEM_NOC_CNOC 24 +#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25 +#define SC8280XP_MASTER_GFX3D 26 +#define SC8280XP_MASTER_LPASS_ANOC 27 +#define SC8280XP_MASTER_MDP0 28 +#define SC8280XP_MASTER_MDP1 29 +#define SC8280XP_MASTER_MDP_CORE1_0 30 +#define SC8280XP_MASTER_MDP_CORE1_1 31 +#define SC8280XP_MASTER_CNOC_MNOC_CFG 32 +#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33 +#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34 +#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35 +#define SC8280XP_MASTER_ROTATOR 36 +#define SC8280XP_MASTER_ROTATOR_1 37 +#define SC8280XP_MASTER_SNOC_CFG 38 +#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39 +#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40 +#define SC8280XP_MASTER_VIDEO_P0 41 +#define SC8280XP_MASTER_VIDEO_P1 42 +#define SC8280XP_MASTER_VIDEO_PROC 43 +#define SC8280XP_MASTER_QUP_CORE_0 44 +#define SC8280XP_MASTER_QUP_CORE_1 45 +#define SC8280XP_MASTER_QUP_CORE_2 46 +#define SC8280XP_MASTER_CAMNOC_ICP 47 +#define SC8280XP_MASTER_CAMNOC_SF 48 +#define SC8280XP_MASTER_CRYPTO 49 +#define SC8280XP_MASTER_IPA 50 +#define SC8280XP_MASTER_LPASS_PROC 51 +#define SC8280XP_MASTER_CDSP_PROC 52 +#define SC8280XP_MASTER_CDSP_PROC_B 53 +#define SC8280XP_MASTER_PIMEM 54 +#define SC8280XP_MASTER_SENSORS_PROC 55 +#define SC8280XP_MASTER_SP 56 +#define SC8280XP_MASTER_EMAC 57 +#define SC8280XP_MASTER_EMAC_1 58 +#define SC8280XP_MASTER_GIC 59 +#define SC8280XP_MASTER_PCIE_0 60 +#define SC8280XP_MASTER_PCIE_1 61 +#define SC8280XP_MASTER_PCIE_2A 62 +#define SC8280XP_MASTER_PCIE_2B 63 +#define SC8280XP_MASTER_PCIE_3A 64 +#define SC8280XP_MASTER_PCIE_3B 65 +#define SC8280XP_MASTER_PCIE_4 66 +#define SC8280XP_MASTER_QDSS_ETR 67 +#define SC8280XP_MASTER_SDCC_2 68 +#define SC8280XP_MASTER_SDCC_4 69 +#define SC8280XP_MASTER_UFS_CARD 70 +#define SC8280XP_MASTER_UFS_MEM 71 +#define SC8280XP_MASTER_USB3_0 72 +#define SC8280XP_MASTER_USB3_1 73 +#define SC8280XP_MASTER_USB3_MP 74 +#define SC8280XP_MASTER_USB4_0 75 +#define SC8280XP_MASTER_USB4_1 76 +#define SC8280XP_SLAVE_EBI1 512 +#define SC8280XP_SLAVE_IPA_CORE 513 +#define SC8280XP_SLAVE_AHB2PHY_0 514 +#define SC8280XP_SLAVE_AHB2PHY_1 515 +#define SC8280XP_SLAVE_AHB2PHY_2 516 +#define SC8280XP_SLAVE_AOSS 517 +#define SC8280XP_SLAVE_APPSS 518 +#define SC8280XP_SLAVE_CAMERA_CFG 519 +#define SC8280XP_SLAVE_CLK_CTL 520 +#define SC8280XP_SLAVE_CDSP_CFG 521 +#define SC8280XP_SLAVE_CDSP1_CFG 522 +#define SC8280XP_SLAVE_RBCPR_CX_CFG 523 +#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524 +#define SC8280XP_SLAVE_RBCPR_MX_CFG 525 +#define SC8280XP_SLAVE_CPR_NSPCX 526 +#define SC8280XP_SLAVE_CRYPTO_0_CFG 527 +#define SC8280XP_SLAVE_CX_RDPM 528 +#define SC8280XP_SLAVE_DCC_CFG 529 +#define SC8280XP_SLAVE_DISPLAY_CFG 530 +#define SC8280XP_SLAVE_DISPLAY1_CFG 531 +#define SC8280XP_SLAVE_EMAC_CFG 532 +#define SC8280XP_SLAVE_EMAC1_CFG 533 +#define SC8280XP_SLAVE_GFX3D_CFG 534 +#define SC8280XP_SLAVE_HWKM 535 +#define SC8280XP_SLAVE_IMEM_CFG 536 +#define SC8280XP_SLAVE_IPA_CFG 537 +#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538 +#define SC8280XP_SLAVE_LLCC_CFG 539 +#define SC8280XP_SLAVE_LPASS 540 +#define SC8280XP_SLAVE_LPASS_CORE_CFG 541 +#define SC8280XP_SLAVE_LPASS_LPI_CFG 542 +#define SC8280XP_SLAVE_LPASS_MPU_CFG 543 +#define SC8280XP_SLAVE_LPASS_TOP_CFG 544 +#define SC8280XP_SLAVE_MX_RDPM 545 +#define SC8280XP_SLAVE_MXC_RDPM 546 +#define SC8280XP_SLAVE_PCIE_0_CFG 547 +#define SC8280XP_SLAVE_PCIE_1_CFG 548 +#define SC8280XP_SLAVE_PCIE_2A_CFG 549 +#define SC8280XP_SLAVE_PCIE_2B_CFG 550 +#define SC8280XP_SLAVE_PCIE_3A_CFG 551 +#define SC8280XP_SLAVE_PCIE_3B_CFG 552 +#define SC8280XP_SLAVE_PCIE_4_CFG 553 +#define SC8280XP_SLAVE_PCIE_RSC_CFG 554 +#define SC8280XP_SLAVE_PDM 555 +#define SC8280XP_SLAVE_PIMEM_CFG 556 +#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557 +#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558 +#define SC8280XP_SLAVE_QDSS_CFG 559 +#define SC8280XP_SLAVE_QSPI_0 560 +#define SC8280XP_SLAVE_QUP_0 561 +#define SC8280XP_SLAVE_QUP_1 562 +#define SC8280XP_SLAVE_QUP_2 563 +#define SC8280XP_SLAVE_SDCC_2 564 +#define SC8280XP_SLAVE_SDCC_4 565 +#define SC8280XP_SLAVE_SECURITY 566 +#define SC8280XP_SLAVE_SMMUV3_CFG 567 +#define SC8280XP_SLAVE_SMSS_CFG 568 +#define SC8280XP_SLAVE_SPSS_CFG 569 +#define SC8280XP_SLAVE_TCSR 570 +#define SC8280XP_SLAVE_TLMM 571 +#define SC8280XP_SLAVE_UFS_CARD_CFG 572 +#define SC8280XP_SLAVE_UFS_MEM_CFG 573 +#define SC8280XP_SLAVE_USB3_0 574 +#define SC8280XP_SLAVE_USB3_1 575 +#define SC8280XP_SLAVE_USB3_MP 576 +#define SC8280XP_SLAVE_USB4_0 577 +#define SC8280XP_SLAVE_USB4_1 578 +#define SC8280XP_SLAVE_VENUS_CFG 579 +#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580 +#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581 +#define SC8280XP_SLAVE_A1NOC_CFG 582 +#define SC8280XP_SLAVE_A1NOC_SNOC 583 +#define SC8280XP_SLAVE_A2NOC_CFG 584 +#define SC8280XP_SLAVE_A2NOC_SNOC 585 +#define SC8280XP_SLAVE_USB_NOC_SNOC 586 +#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587 +#define SC8280XP_SLAVE_DDRSS_CFG 588 +#define SC8280XP_SLAVE_GEM_NOC_CNOC 589 +#define SC8280XP_SLAVE_GEM_NOC_CFG 590 +#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591 +#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592 +#define SC8280XP_SLAVE_LLCC 593 +#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594 +#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595 +#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596 +#define SC8280XP_SLAVE_CDSP_MEM_NOC 597 +#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598 +#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599 +#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600 +#define SC8280XP_SLAVE_SNOC_CFG 601 +#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602 +#define SC8280XP_SLAVE_LPASS_SNOC 603 +#define SC8280XP_SLAVE_QUP_CORE_0 604 +#define SC8280XP_SLAVE_QUP_CORE_1 605 +#define SC8280XP_SLAVE_QUP_CORE_2 606 +#define SC8280XP_SLAVE_IMEM 607 +#define SC8280XP_SLAVE_NSP_XFR 608 +#define SC8280XP_SLAVE_NSPB_XFR 609 +#define SC8280XP_SLAVE_PIMEM 610 +#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611 +#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612 +#define SC8280XP_SLAVE_SERVICE_A1NOC 613 +#define SC8280XP_SLAVE_SERVICE_A2NOC 614 +#define SC8280XP_SLAVE_SERVICE_CNOC 615 +#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616 +#define SC8280XP_SLAVE_SERVICE_MNOC 617 +#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618 +#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619 +#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620 +#define SC8280XP_SLAVE_SERVICE_SNOC 621 +#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622 +#define SC8280XP_SLAVE_PCIE_0 623 +#define SC8280XP_SLAVE_PCIE_1 624 +#define SC8280XP_SLAVE_PCIE_2A 625 +#define SC8280XP_SLAVE_PCIE_2B 626 +#define SC8280XP_SLAVE_PCIE_3A 627 +#define SC8280XP_SLAVE_PCIE_3B 628 +#define SC8280XP_SLAVE_PCIE_4 629 +#define SC8280XP_SLAVE_QDSS_STM 630 +#define SC8280XP_SLAVE_SMSS 631 +#define SC8280XP_SLAVE_TCU 632 + +#endif + diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 274a7139fe1a..8d879b0bcabc 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1490,7 +1490,7 @@ static struct qcom_icc_node slv_srvc_snoc = { .slv_rpm_id = 29, }; -static struct qcom_icc_node *sdm660_a2noc_nodes[] = { +static struct qcom_icc_node * const sdm660_a2noc_nodes[] = { [MASTER_IPA] = &mas_ipa, [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, [MASTER_SDCC_1] = &mas_sdcc_1, @@ -1512,7 +1512,7 @@ static const struct regmap_config sdm660_a2noc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_a2noc = { +static const struct qcom_icc_desc sdm660_a2noc = { .type = QCOM_ICC_NOC, .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), @@ -1521,7 +1521,7 @@ static struct qcom_icc_desc sdm660_a2noc = { .regmap_cfg = &sdm660_a2noc_regmap_config, }; -static struct qcom_icc_node *sdm660_bimc_nodes[] = { +static struct qcom_icc_node * const sdm660_bimc_nodes[] = { [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, [MASTER_OXILI] = &mas_oxili, [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, @@ -1540,14 +1540,14 @@ static const struct regmap_config sdm660_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_bimc = { +static const struct qcom_icc_desc sdm660_bimc = { .type = QCOM_ICC_BIMC, .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), .regmap_cfg = &sdm660_bimc_regmap_config, }; -static struct qcom_icc_node *sdm660_cnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, @@ -1594,14 +1594,14 @@ static const struct regmap_config sdm660_cnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_cnoc = { +static const struct qcom_icc_desc sdm660_cnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_cnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), .regmap_cfg = &sdm660_cnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_gnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_gnoc_nodes[] = { [MASTER_APSS_PROC] = &mas_apss_proc, [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc, @@ -1615,14 +1615,14 @@ static const struct regmap_config sdm660_gnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_gnoc = { +static const struct qcom_icc_desc sdm660_gnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_gnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), .regmap_cfg = &sdm660_gnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_mnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_mnoc_nodes[] = { [MASTER_CPP] = &mas_cpp, [MASTER_JPEG] = &mas_jpeg, [MASTER_MDP_P0] = &mas_mdp_p0, @@ -1655,7 +1655,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_mnoc = { +static const struct qcom_icc_desc sdm660_mnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), @@ -1664,7 +1664,7 @@ static struct qcom_icc_desc sdm660_mnoc = { .regmap_cfg = &sdm660_mnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_snoc_nodes[] = { +static struct qcom_icc_node * const sdm660_snoc_nodes[] = { [MASTER_QDSS_ETR] = &mas_qdss_etr, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_SNOC_CFG] = &mas_snoc_cfg, @@ -1692,7 +1692,7 @@ static const struct regmap_config sdm660_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_snoc = { +static const struct qcom_icc_desc sdm660_snoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_snoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index d2195079c228..954e7bd13fc4 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -175,12 +175,12 @@ DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn9, &bcm_qup0, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_TSIF] = &qhm_tsif, [MASTER_SDCC_2] = &xm_sdc2, @@ -201,13 +201,13 @@ static const struct qcom_icc_desc sdm845_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_sn11, &bcm_qup0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_CNOC_A2NOC] = &qnm_cnoc, @@ -230,11 +230,11 @@ static const struct qcom_icc_desc sdm845_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SPDM] = &qhm_spdm, [MASTER_TIC] = &qhm_tic, [MASTER_SNOC_CNOC] = &qnm_snoc, @@ -291,10 +291,10 @@ static const struct qcom_icc_desc sdm845_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, @@ -307,10 +307,10 @@ static const struct qcom_icc_desc sdm845_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gladiator_noc_bcms[] = { +static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { }; -static struct qcom_icc_node *gladiator_noc_nodes[] = { +static struct qcom_icc_node * const gladiator_noc_nodes[] = { [MASTER_APPSS_PROC] = &acm_l3, [MASTER_GNOC_CFG] = &pm_gnoc_cfg, [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, @@ -325,7 +325,7 @@ static const struct qcom_icc_desc sdm845_gladiator_noc = { .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), }; -static struct qcom_icc_bcm *mem_noc_bcms[] = { +static struct qcom_icc_bcm * const mem_noc_bcms[] = { &bcm_mc0, &bcm_acv, &bcm_sh0, @@ -335,7 +335,7 @@ static struct qcom_icc_bcm *mem_noc_bcms[] = { &bcm_sh5, }; -static struct qcom_icc_node *mem_noc_nodes[] = { +static struct qcom_icc_node * const mem_noc_nodes[] = { [MASTER_TCU_0] = &acm_tcu, [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, [MASTER_GNOC_MEM_NOC] = &qnm_apps, @@ -360,14 +360,14 @@ static const struct qcom_icc_desc sdm845_mem_noc = { .num_bcms = ARRAY_SIZE(mem_noc_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -394,7 +394,7 @@ static const struct qcom_icc_desc sdm845_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, @@ -411,7 +411,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn15, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index e3ac25a997b7..130a828c3873 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -99,11 +99,11 @@ DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; @@ -115,13 +115,13 @@ static const struct qcom_icc_desc sdx55_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mem_noc_bcms[] = { +static struct qcom_icc_bcm * const mem_noc_bcms[] = { &bcm_sh0, &bcm_sh3, &bcm_sh4, }; -static struct qcom_icc_node *mem_noc_nodes[] = { +static struct qcom_icc_node * const mem_noc_nodes[] = { [MASTER_TCU_0] = &acm_tcu, [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, [MASTER_AMPSS_M0] = &xm_apps_rdwr, @@ -137,7 +137,7 @@ static const struct qcom_icc_desc sdx55_mem_noc = { .num_bcms = ARRAY_SIZE(mem_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_ce0, &bcm_pn0, &bcm_pn1, @@ -156,7 +156,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn11, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_AUDIO] = &qhm_audio, [MASTER_BLSP_1] = &qhm_blsp1, [MASTER_QDSS_BAM] = &qhm_qdss_bam, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c new file mode 100644 index 000000000000..b16d31d53e9b --- /dev/null +++ b/drivers/interconnect/qcom/sdx65.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sdx65.h" + +DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); +DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); +DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC); +DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); +DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); +DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC); +DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); +DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); +DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0); +DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0); +DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); +DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); +DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); +DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); +DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC); +DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC); +DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); +DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); +DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); +DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); +DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); +DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); +DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); +DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); +DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); +DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); +DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); +DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); +DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); +DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); +DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); +DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); +DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG); +DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); +DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); +DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); +DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); +DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); +DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); +DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC); +DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC); +DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); +DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); +DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); +DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); +DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); + +DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); +DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); +DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc); +DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); +DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); +DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); +DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); +DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); +DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); +DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); +DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); +DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); +DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); +DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); +DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); +DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); +DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc); +DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); +DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); +DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sdx65_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, + &bcm_sh3, +}; + +static struct qcom_icc_node * const mem_noc_nodes[] = { + [MASTER_TCU_0] = &acm_tcu, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_APPSS_PROC] = &xm_apps_rdwr, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, +}; + +static const struct qcom_icc_desc sdx65_mem_noc = { + .nodes = mem_noc_nodes, + .num_nodes = ARRAY_SIZE(mem_noc_nodes), + .bcms = mem_noc_bcms, + .num_bcms = ARRAY_SIZE(mem_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_ce0, + &bcm_pn0, + &bcm_pn1, + &bcm_pn2, + &bcm_pn3, + &bcm_pn4, + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn5, + &bcm_sn6, + &bcm_sn7, + &bcm_sn8, + &bcm_sn9, + &bcm_sn10, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_AUDIO] = &qhm_audio, + [MASTER_BLSP_1] = &qhm_blsp1, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QPIC] = &qhm_qpic, + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, + [MASTER_ANOC_SNOC] = &qnm_aggre_noc, + [MASTER_IPA] = &qnm_ipa, + [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, + [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, + [MASTER_PCIE_0] = &xm_pcie, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_USB3] = &xm_usb3, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_AUDIO] = &qhs_audio, + [SLAVE_BLSP_1] = &qhs_blsp1, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, + [SLAVE_ECC_CFG] = &qhs_ecc_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_PCIE_PARF] = &qhs_pcie_parf, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QPIC] = &qhs_qpic, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, + [SLAVE_ANOC_SNOC] = &qns_aggre_noc, + [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_PCIE_0] = &xs_pcie, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sdx65_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sdx65-mc-virt", + .data = &sdx65_mc_virt}, + { .compatible = "qcom,sdx65-mem-noc", + .data = &sdx65_mem_noc}, + { .compatible = "qcom,sdx65-system-noc", + .data = &sdx65_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sdx65", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; +module_platform_driver(qnoc_driver); + +MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/sdx65.h b/drivers/interconnect/qcom/sdx65.h new file mode 100644 index 000000000000..5dca6e8b32c9 --- /dev/null +++ b/drivers/interconnect/qcom/sdx65.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H +#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H + +#define SDX65_MASTER_TCU_0 0 +#define SDX65_MASTER_LLCC 1 +#define SDX65_MASTER_AUDIO 2 +#define SDX65_MASTER_BLSP_1 3 +#define SDX65_MASTER_QDSS_BAM 4 +#define SDX65_MASTER_QPIC 5 +#define SDX65_MASTER_SNOC_CFG 6 +#define SDX65_MASTER_SPMI_FETCHER 7 +#define SDX65_MASTER_ANOC_SNOC 8 +#define SDX65_MASTER_IPA 9 +#define SDX65_MASTER_MEM_NOC_SNOC 10 +#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11 +#define SDX65_MASTER_SNOC_GC_MEM_NOC 12 +#define SDX65_MASTER_CRYPTO 13 +#define SDX65_MASTER_APPSS_PROC 14 +#define SDX65_MASTER_IPA_PCIE 15 +#define SDX65_MASTER_PCIE_0 16 +#define SDX65_MASTER_QDSS_ETR 17 +#define SDX65_MASTER_SDCC_1 18 +#define SDX65_MASTER_USB3 19 +#define SDX65_SLAVE_EBI1 512 +#define SDX65_SLAVE_AOSS 513 +#define SDX65_SLAVE_APPSS 514 +#define SDX65_SLAVE_AUDIO 515 +#define SDX65_SLAVE_BLSP_1 516 +#define SDX65_SLAVE_CLK_CTL 517 +#define SDX65_SLAVE_CRYPTO_0_CFG 518 +#define SDX65_SLAVE_CNOC_DDRSS 519 +#define SDX65_SLAVE_ECC_CFG 520 +#define SDX65_SLAVE_IMEM_CFG 521 +#define SDX65_SLAVE_IPA_CFG 522 +#define SDX65_SLAVE_CNOC_MSS 523 +#define SDX65_SLAVE_PCIE_PARF 524 +#define SDX65_SLAVE_PDM 525 +#define SDX65_SLAVE_PRNG 526 +#define SDX65_SLAVE_QDSS_CFG 527 +#define SDX65_SLAVE_QPIC 528 +#define SDX65_SLAVE_SDCC_1 529 +#define SDX65_SLAVE_SNOC_CFG 530 +#define SDX65_SLAVE_SPMI_FETCHER 531 +#define SDX65_SLAVE_SPMI_VGI_COEX 532 +#define SDX65_SLAVE_TCSR 533 +#define SDX65_SLAVE_TLMM 534 +#define SDX65_SLAVE_USB3 535 +#define SDX65_SLAVE_USB3_PHY_CFG 536 +#define SDX65_SLAVE_ANOC_SNOC 537 +#define SDX65_SLAVE_LLCC 538 +#define SDX65_SLAVE_MEM_NOC_SNOC 539 +#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540 +#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541 +#define SDX65_SLAVE_IMEM 542 +#define SDX65_SLAVE_SERVICE_SNOC 543 +#define SDX65_SLAVE_PCIE_0 544 +#define SDX65_SLAVE_QDSS_STM 545 +#define SDX65_SLAVE_TCU 546 + +#endif diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 745e3c36a61a..1d04a4bfea80 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -186,12 +186,12 @@ DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic); DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, &bcm_sn3, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QUP_0] = &qhm_qup0, [MASTER_EMAC] = &xm_emac, @@ -202,21 +202,21 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8150_aggre1_noc = { +static const struct qcom_icc_desc sm8150_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_qup0, &bcm_sn14, &bcm_sn3, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QSPI] = &qhm_qspi, @@ -237,53 +237,53 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8150_aggre2_noc = { +static const struct qcom_icc_desc sm8150_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, }; -static struct qcom_icc_desc sm8150_camnoc_virt = { +static const struct qcom_icc_desc sm8150_camnoc_virt = { .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co1, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; -static struct qcom_icc_desc sm8150_compute_noc = { +static const struct qcom_icc_desc sm8150_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SPDM] = &qhm_spdm, [SNOC_CNOC_MAS] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, @@ -340,30 +340,30 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sm8150_config_noc = { +static const struct qcom_icc_desc sm8150_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, }; -static struct qcom_icc_desc sm8150_dc_noc = { +static const struct qcom_icc_desc sm8150_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -371,7 +371,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh5, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_AMPSS_M0] = &acm_apps, [MASTER_GPU_TCU] = &acm_gpu_tcu, [MASTER_SYS_TCU] = &acm_sys_tcu, @@ -391,54 +391,54 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; -static struct qcom_icc_desc sm8150_gem_noc = { +static const struct qcom_icc_desc sm8150_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; -static struct qcom_icc_desc sm8150_ipa_virt = { +static const struct qcom_icc_desc sm8150_ipa_virt = { .nodes = ipa_virt_nodes, .num_nodes = ARRAY_SIZE(ipa_virt_nodes), .bcms = ipa_virt_bcms, .num_bcms = ARRAY_SIZE(ipa_virt_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; -static struct qcom_icc_desc sm8150_mc_virt = { +static const struct qcom_icc_desc sm8150_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -454,14 +454,14 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sm8150_mmss_noc = { +static const struct qcom_icc_desc sm8150_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn11, @@ -475,7 +475,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn9, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, @@ -495,7 +495,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8150_system_noc = { +static const struct qcom_icc_desc sm8150_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index aa707582ea01..5cdb058fa095 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -195,12 +195,12 @@ DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie); DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, &bcm_sn12, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, @@ -216,20 +216,20 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8250_aggre1_noc = { +static const struct qcom_icc_desc sm8250_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_qup0, &bcm_sn12, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, @@ -246,35 +246,35 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8250_aggre2_noc = { +static const struct qcom_icc_desc sm8250_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; -static struct qcom_icc_desc sm8250_compute_noc = { +static const struct qcom_icc_desc sm8250_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [SNOC_CNOC_MAS] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, @@ -329,37 +329,37 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sm8250_config_noc = { +static const struct qcom_icc_desc sm8250_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, }; -static struct qcom_icc_desc sm8250_dc_noc = { +static const struct qcom_icc_desc sm8250_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_AMPSS_M0] = &chm_apps, @@ -379,54 +379,54 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, }; -static struct qcom_icc_desc sm8250_gem_noc = { +static const struct qcom_icc_desc sm8250_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; -static struct qcom_icc_desc sm8250_ipa_virt = { +static const struct qcom_icc_desc sm8250_ipa_virt = { .nodes = ipa_virt_nodes, .num_nodes = ARRAY_SIZE(ipa_virt_nodes), .bcms = ipa_virt_bcms, .num_bcms = ARRAY_SIZE(ipa_virt_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; -static struct qcom_icc_desc sm8250_mc_virt = { +static const struct qcom_icc_desc sm8250_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, @@ -442,17 +442,17 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sm8250_mmss_noc = { +static const struct qcom_icc_desc sm8250_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *npu_noc_bcms[] = { +static struct qcom_icc_bcm * const npu_noc_bcms[] = { }; -static struct qcom_icc_node *npu_noc_nodes[] = { +static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w, [MASTER_NPU_NOC_CFG] = &qhm_cfg, @@ -468,14 +468,14 @@ static struct qcom_icc_node *npu_noc_nodes[] = { [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, }; -static struct qcom_icc_desc sm8250_npu_noc = { +static const struct qcom_icc_desc sm8250_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), .bcms = npu_noc_bcms, .num_bcms = ARRAY_SIZE(npu_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn11, @@ -489,7 +489,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn9, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, @@ -511,7 +511,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8250_system_noc = { +static const struct qcom_icc_desc sm8250_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index c79f93a1ac73..5398e7c8d826 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -198,10 +198,10 @@ DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, @@ -213,21 +213,21 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8350_aggre1_noc = { +static const struct qcom_icc_desc sm8350_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_sn5, &bcm_sn6, &bcm_sn14, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_2] = &qhm_qup2, @@ -244,14 +244,14 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8350_aggre2_noc = { +static const struct qcom_icc_desc sm8350_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, &bcm_cn1, &bcm_cn2, @@ -259,7 +259,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_sn4, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [MASTER_QDSS_DAP] = &xm_qdss_dap, @@ -323,30 +323,30 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8350_config_noc = { +static const struct qcom_icc_desc sm8350_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; -static struct qcom_icc_desc sm8350_dc_noc = { +static const struct qcom_icc_desc sm8350_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -354,7 +354,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh0_disp, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -379,17 +379,17 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_LLCC_DISP] = &qns_llcc_disp, }; -static struct qcom_icc_desc sm8350_gem_noc = { +static const struct qcom_icc_desc sm8350_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, @@ -399,35 +399,35 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sm8350_lpass_ag_noc = { +static const struct qcom_icc_desc sm8350_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_acv_disp, &bcm_mc0_disp, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, [MASTER_LLCC_DISP] = &llcc_mc_disp, [SLAVE_EBI1_DISP] = &ebi_disp, }; -static struct qcom_icc_desc sm8350_mc_virt = { +static const struct qcom_icc_desc sm8350_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm4, @@ -438,7 +438,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm5_disp, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, @@ -459,40 +459,40 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, }; -static struct qcom_icc_desc sm8350_mmss_noc = { +static const struct qcom_icc_desc sm8350_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, &bcm_co3, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sm8350_compute_noc = { +static const struct qcom_icc_desc sm8350_compute_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn2, &bcm_sn7, &bcm_sn8, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [MASTER_SNOC_CFG] = &qnm_snoc_cfg, @@ -503,7 +503,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sm8350_system_noc = { +static const struct qcom_icc_desc sm8350_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 8d99ee6421df..7e3d372b712f 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1526,10 +1526,10 @@ static struct qcom_icc_bcm bcm_sh1_disp = { .nodes = { &qnm_pcie_disp }, }; -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, @@ -1540,18 +1540,18 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8450_aggre1_noc = { +static const struct qcom_icc_desc sm8450_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_2] = &qhm_qup2, @@ -1567,20 +1567,20 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8450_aggre2_noc = { +static const struct qcom_icc_desc sm8450_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *clk_virt_bcms[] = { +static struct qcom_icc_bcm * const clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, &bcm_qup2, }; -static struct qcom_icc_node *clk_virt_nodes[] = { +static struct qcom_icc_node * const clk_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [MASTER_QUP_CORE_2] = &qup2_core_master, @@ -1589,18 +1589,18 @@ static struct qcom_icc_node *clk_virt_nodes[] = { [SLAVE_QUP_CORE_2] = &qup2_core_slave, }; -static struct qcom_icc_desc sm8450_clk_virt = { +static const struct qcom_icc_desc sm8450_clk_virt = { .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, @@ -1658,21 +1658,21 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8450_config_noc = { +static const struct qcom_icc_desc sm8450_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, &bcm_sh0_disp, &bcm_sh1_disp, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -1693,17 +1693,17 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_LLCC_DISP] = &qns_llcc_disp, }; -static struct qcom_icc_desc sm8450_gem_noc = { +static const struct qcom_icc_desc sm8450_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [MASTER_LPASS_PROC] = &qxm_lpass_dsp, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, @@ -1715,42 +1715,42 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sm8450_lpass_ag_noc = { +static const struct qcom_icc_desc sm8450_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_acv_disp, &bcm_mc0_disp, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, [MASTER_LLCC_DISP] = &llcc_mc_disp, [SLAVE_EBI1_DISP] = &ebi_disp, }; -static struct qcom_icc_desc sm8450_mc_virt = { +static const struct qcom_icc_desc sm8450_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm0_disp, &bcm_mm1_disp, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, @@ -1771,36 +1771,36 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, }; -static struct qcom_icc_desc sm8450_mmss_noc = { +static const struct qcom_icc_desc sm8450_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sm8450_nsp_noc = { +static const struct qcom_icc_desc sm8450_nsp_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *pcie_anoc_bcms[] = { +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { &bcm_sn7, }; -static struct qcom_icc_node *pcie_anoc_nodes[] = { +static struct qcom_icc_node * const pcie_anoc_nodes[] = { [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, [MASTER_PCIE_0] = &xm_pcie3_0, [MASTER_PCIE_1] = &xm_pcie3_1, @@ -1808,14 +1808,14 @@ static struct qcom_icc_node *pcie_anoc_nodes[] = { [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, }; -static struct qcom_icc_desc sm8450_pcie_anoc = { +static const struct qcom_icc_desc sm8450_pcie_anoc = { .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, @@ -1823,7 +1823,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn4, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_GIC_AHB] = &qhm_gic, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, @@ -1836,7 +1836,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sm8450_system_noc = { +static const struct qcom_icc_desc sm8450_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1848,7 +1848,7 @@ static int qnoc_probe(struct platform_device *pdev) const struct qcom_icc_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes; + struct qcom_icc_node * const *qnodes; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; |