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| author | Qiuxu Zhuo <qiuxu.zhuo@intel.com> | 2020-11-17 15:49:53 +0300 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2020-11-19 23:57:26 +0300 |
| commit | 479f58dda25bb46daeb937f124718e8b4aea6781 (patch) | |
| tree | 0758d1cde52a57ffd48e5b9909767973a55beb56 /drivers/interconnect/core.c | |
| parent | bc1c99a5971aa7571e8b9731c28fa32abe12cab8 (diff) | |
| download | linux-479f58dda25bb46daeb937f124718e8b4aea6781.tar.xz | |
EDAC/i10nm: Add Intel Sapphire Rapids server support
The Sapphire Rapids CPU model shares the same memory controller
architecture with Ice Lake server. There are some configurations
different from Ice Lake server as below:
- The device ID for configuration agent.
- The size for per channel memory-mapped I/O.
- The DDR5 memory support.
So add the above configurations and the Sapphire Rapids CPU model
ID for EDAC support.
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'drivers/interconnect/core.c')
0 files changed, 0 insertions, 0 deletions