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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 20:56:23 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 13:53:15 +0300 |
| commit | 8779b88c214fa0f8fdfb9c54a124f468884d356a (patch) | |
| tree | 631a09c46decbd138f7b8d7259743e2ab93b2aea /drivers/iio/dac | |
| parent | 314d2b1978bb3d20b1ec239f4e28c394da493f36 (diff) | |
| download | linux-8779b88c214fa0f8fdfb9c54a124f468884d356a.tar.xz | |
iio: dac: ad5064: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 6a17a0768f77 ("iio:dac:ad5064: Add support for the ad5629r and ad5669r")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-44-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
| -rw-r--r-- | drivers/iio/dac/ad5064.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/dac/ad5064.c b/drivers/iio/dac/ad5064.c index d87cf14daabe..4447b8811827 100644 --- a/drivers/iio/dac/ad5064.c +++ b/drivers/iio/dac/ad5064.c @@ -115,13 +115,13 @@ struct ad5064_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { u8 i2c[3]; __be32 spi; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; enum ad5064_type { |