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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 20:55:50 +0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 13:53:12 +0300
commit4e2008429588b857bbc13d048b67b931a8d84816 (patch)
tree32062d2a709a7f42d31b99f5b9b2f5fe1faf1f54 /drivers/iio/adc
parentb990cdfe7536a8da7e134d516350402981300016 (diff)
downloadlinux-4e2008429588b857bbc13d048b67b931a8d84816.tar.xz
iio: adc: ad7280a: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 003f1d48de52 ("staging:iio:adc:ad7280a: Split buff[2] into tx and rx parts") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-11-jic23@kernel.org
Diffstat (limited to 'drivers/iio/adc')
-rw-r--r--drivers/iio/adc/ad7280a.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/ad7280a.c b/drivers/iio/adc/ad7280a.c
index 3bdf3d9422f2..d4a4e15c8244 100644
--- a/drivers/iio/adc/ad7280a.c
+++ b/drivers/iio/adc/ad7280a.c
@@ -183,7 +183,7 @@ struct ad7280_state {
unsigned char cb_mask[AD7280A_MAX_CHAIN];
struct mutex lock; /* protect sensor state */
- __be32 tx ____cacheline_aligned;
+ __be32 tx __aligned(IIO_DMA_MINALIGN);
__be32 rx;
};