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authorGeorge Stark <gnstark@sberdevices.ru>2023-07-15 14:05:58 +0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2023-07-22 19:58:23 +0300
commit6ad9f01cf4fc2b51504ce45080e379ad5a204d76 (patch)
tree108fcebfd6023c019a2560b7fbc29c6b99cdd776 /drivers/iio/adc
parentad25fc289be9532f486ef2cc6156e8d5acb060db (diff)
downloadlinux-6ad9f01cf4fc2b51504ce45080e379ad5a204d76.tar.xz
iio: adc: meson: init channels 0,1 input muxes
Set up input channels 0,1 muxes in the same way as for the channels 2-7 later in the code. Signed-off-by: George Stark <gnstark@sberdevices.ru> Link: https://lore.kernel.org/r/20230715110654.6035-2-gnstark@sberdevices.ru Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc')
-rw-r--r--drivers/iio/adc/meson_saradc.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 81659c0abf6c..650ab9390514 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -899,6 +899,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
regval);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
+
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
+ MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
+
/*
* set up the input channel muxes in MESON_SAR_ADC_AUX_SW
* (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable