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authorArtem Bityutskiy <artem.bityutskiy@linux.intel.com>2022-03-02 11:16:00 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2022-03-04 21:54:32 +0300
commit3a9cf77b60dc9839b6674943bb7c9dcd524b6294 (patch)
tree72b57b5e202ebf70230baceb1bde4ebe9facaee0 /drivers/idle
parentda0e58c038e60e7e65d30813ebdfe91687aa8a24 (diff)
downloadlinux-3a9cf77b60dc9839b6674943bb7c9dcd524b6294.tar.xz
intel_idle: add core C6 optimization for SPR
Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to match core C6 values, instead of using the default package C6 values. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/idle')
-rw-r--r--drivers/idle/intel_idle.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index b2688c326522..e385ddf15b32 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1578,6 +1578,8 @@ static void __init skx_idle_state_table_update(void)
*/
static void __init spr_idle_state_table_update(void)
{
+ unsigned long long msr;
+
/* Check if user prefers C1E over C1. */
if (preferred_states_mask & BIT(2)) {
if (preferred_states_mask & BIT(1))
@@ -1591,6 +1593,19 @@ static void __init spr_idle_state_table_update(void)
c1e_promotion_enable();
disable_promotion_to_c1e = false;
}
+
+ /*
+ * By default, the C6 state assumes the worst-case scenario of package
+ * C6. However, if PC6 is disabled, we update the numbers to match
+ * core C6.
+ */
+ rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
+
+ /* Limit value 2 and above allow for PC6. */
+ if ((msr & 0x7) < 2) {
+ spr_cstates[2].exit_latency = 190;
+ spr_cstates[2].target_residency = 600;
+ }
}
static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)