diff options
author | Frank Crawford <frank@crawford.emu.id.au> | 2024-04-28 09:06:35 +0300 |
---|---|---|
committer | Guenter Roeck <linux@roeck-us.net> | 2024-04-30 20:32:14 +0300 |
commit | e58095cfc55692e4da4a5e87322e09a9b75186e0 (patch) | |
tree | ae8fce4fa0a805acbfecd60d0356a96713fc4e85 /drivers/hwmon | |
parent | e2e6a23f4bda2de9c7096aa9c310bc3400187e90 (diff) | |
download | linux-e58095cfc55692e4da4a5e87322e09a9b75186e0.tar.xz |
hwmon: (it87) Test for chipset before entering configuration mode
Major part of the change for the new method to avoid chipset issues.
The actual update does the following:
1) Lock the memory, but does not perform a SIO entry (previously it
would have performed an SIO entry).
2) Attempt to read the chipID. This should be safe no matter which
chip we have.
3) If step (2) fails, then perform SIO entry and retry chipID read. For
older chips and on failure it acts similarly to prior to this patch.
4) Set the sio_data->type, similar to previously.
5) If we have not performed an SIO entry, and this is not a chip type
with the NOCONF feature, then it will perform an SIO entry at this
point.
6) Proceed with setup as prior to this patch.
7) Any following access to the SIO registers will invoke the SIO entry
and SIO exit steps unless it is a chip with the NOCONF feature set.
This was set up in the previous patches in this patchset.
8) Update to the exit based on if it had performed a SIO entry or not.
Signed-off-by: Frank Crawford <frank@crawford.emu.id.au>
Link: https://lore.kernel.org/r/20240428060653.2425296-4-frank@crawford.emu.id.au
[groeck: s/intialised/initialized/]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'drivers/hwmon')
-rw-r--r-- | drivers/hwmon/it87.c | 52 |
1 files changed, 47 insertions, 5 deletions
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 702a3752a211..47eeff4a692a 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -2667,6 +2667,27 @@ static const struct attribute_group it87_group_auto_pwm = { .is_visible = it87_auto_pwm_is_visible, }; +/* + * Original explanation: + * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip + * (IT8792E) needs to be in configuration mode before accessing the first + * due to a bug in IT8792E which otherwise results in LPC bus access errors. + * This needs to be done before accessing the first Super-IO chip since + * the second chip may have been accessed prior to loading this driver. + * + * The problem is also reported to affect IT8795E, which is used on X299 boards + * and has the same chip ID as IT8792E (0x8733). It also appears to affect + * systems with IT8790E, which is used on some Z97X-Gaming boards as well as + * Z87X-OC. + * + * From other information supplied: + * ChipIDs 0x8733, 0x8695 (early ID for IT87952E) and 0x8790 are initialized + * and left in configuration mode, and entering and/or exiting configuration + * mode is what causes the crash. + * + * The recommendation is to look up the chipID before doing any mode swap + * and then act accordingly. + */ /* SuperIO detection - will change isa_address if a chip is found */ static int __init it87_find(int sioaddr, unsigned short *address, struct it87_sio_data *sio_data, int chip_cnt) @@ -2674,16 +2695,25 @@ static int __init it87_find(int sioaddr, unsigned short *address, int err; u16 chip_type; const struct it87_devices *config = NULL; + bool enabled = false; - err = superio_enter(sioaddr, false); + /* First step, lock memory but don't enter configuration mode */ + err = superio_enter(sioaddr, true); if (err) return err; err = -ENODEV; chip_type = superio_inw(sioaddr, DEVID); - /* check first for a valid chip before forcing chip id */ - if (chip_type == 0xffff) - goto exit; + /* Check for a valid chip before forcing chip id */ + if (chip_type == 0xffff) { + /* Enter configuration mode */ + __superio_enter(sioaddr); + enabled = true; + /* and then try again */ + chip_type = superio_inw(sioaddr, DEVID); + if (chip_type == 0xffff) + goto exit; + } if (force_id_cnt == 1) { /* If only one value given use for all chips */ @@ -2767,6 +2797,18 @@ static int __init it87_find(int sioaddr, unsigned short *address, config = &it87_devices[sio_data->type]; + /* + * If previously we didn't enter configuration mode and it isn't a + * chip we know is initialised in configuration mode, then enter + * configuration mode. + * + * I don't know if any such chips can exist but be defensive. + */ + if (!enabled && !has_noconf(config)) { + __superio_enter(sioaddr); + enabled = true; + } + superio_select(sioaddr, PME); if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", @@ -3144,7 +3186,7 @@ static int __init it87_find(int sioaddr, unsigned short *address, } exit: - superio_exit(sioaddr, config ? has_noconf(config) : false); + superio_exit(sioaddr, !enabled); return err; } |