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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2020-11-16 13:10:02 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-12-10 10:34:01 +0300
commit40745482eec81bea686cd1b38693191dc7e9ac66 (patch)
tree8dc027b75641f4813bbe7e907debc6e2b65fbd2b /drivers/greybus
parent14653942de7f63e21ece32e3901f09a248598a43 (diff)
downloadlinux-40745482eec81bea686cd1b38693191dc7e9ac66.tar.xz
clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR driver. Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC), parent and the divider is set based on the register value CPG_RPCCKCR[4:3] which has been set prior to booting the kernel. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201116101002.5986-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/greybus')
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