diff options
| author | Karl Beldan <kbeldan@baylibre.com> | 2016-08-23 15:56:59 +0300 |
|---|---|---|
| committer | Jyri Sarha <jsarha@ti.com> | 2016-09-01 22:29:12 +0300 |
| commit | ee8c42baebfa28fddb0d0657a87444a1ef3806ed (patch) | |
| tree | 5b01bdd8cf46e6a8f0088713e1d031d2b564aceb /drivers/gpu | |
| parent | a3479c4fa0f149d9f3f6f88c173c4f4cd07a1714 (diff) | |
| download | linux-ee8c42baebfa28fddb0d0657a87444a1ef3806ed.tar.xz | |
drm/tilcdc: Adjust the FB_CEILING address
The LCDC seems to expect its framebuffer ceiling address pointer to be
an inclusive bound. The IP rev2 seems to cope with that but rev1 (as
found on the LCDK) don't.
Also note that this is what the framebuffer code does in da8xx-fb.c.
Since, as the TRM puts it, "The 2 LSBs are hardwired to 00b", the
dma_addr_t can be decremented without cast.
I tested it with a v2 (AM335x, rev 0x4F201000) and an LCDK (v1).
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 25d6b220ee8a..89d69169dada 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -80,7 +80,7 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) end = start + (crtc->mode.vdisplay * fb->pitches[0]); tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start); - tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end); + tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end - 1); if (tilcdc_crtc->curr_fb) drm_flip_work_queue(&tilcdc_crtc->unref_work, |