diff options
| author | Windsome Zeng <windsome.zeng@starfivetech.com> | 2023-10-24 08:48:08 +0300 |
|---|---|---|
| committer | Windsome Zeng <windsome.zeng@starfivetech.com> | 2023-10-24 08:59:38 +0300 |
| commit | b4270330482e37e7ea68ad51d110e56107c93279 (patch) | |
| tree | 925565453d497e76e1cab3e8c35afd31ac7fb44c /drivers/gpu | |
| parent | 214d5e31d666e098d4bd9902595d236ead4addb7 (diff) | |
| download | linux-b4270330482e37e7ea68ad51d110e56107c93279.tar.xz | |
Revert to original code to avoid possible mosaic problem.
Signed-off-by: Windsome Zeng <windsome.zeng@starfivetech.com>
(cherry picked from commit a06cd73561124952dc5ac549d435a8436142c7b5)
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/verisilicon/vs_dc.c | 43 |
1 files changed, 5 insertions, 38 deletions
diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 2a72ae4cd8a5..c72b2e1faf41 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -35,12 +35,6 @@ #define CURSOR_MEM_SIZE_32X32 (32*32*4) #define CURSOR_MEM_SIZE_64X64 (CURSOR_MEM_SIZE_32X32 << 2) -static u32 l2_cache_size = 0; - -static const struct of_device_id sifive_l2_ids[] = { - { .compatible = "sifive,fu740-c000-ccache" }, - { /* end of table */ }, -}; static inline void update_format(u32 format, u64 mod, struct dc_hw_fb *fb) { @@ -653,23 +647,11 @@ static void dc_deinit(struct device *dev) static int dc_init(struct device *dev) { - struct device_node *np; struct vs_dc *dc = dev_get_drvdata(dev); int ret; dc->first_frame = true; - np = of_find_matching_node(NULL, sifive_l2_ids); - if (!np) - return -ENODEV; - - ret = of_property_read_u32(np, "cache-size", &l2_cache_size); - if (ret) { - dev_err(dev, "failed to get l2 cache size\n"); - return ret; - } - l2_cache_size <<= 4; - ret = syscon_panel_parse_dt(dev); if (ret){ dev_err(dev,"syscon_panel_parse_dt failed\n"); @@ -1026,26 +1008,11 @@ static void update_fb(struct vs_plane *plane, u8 display_id, update_swizzle(drm_fb->format->format, fb); update_watermark(plane_state->watermark, fb); - if (fb->enable) { - u32 flush_addr, flush_size; - -#define FLUSH_FB_PLANE(addr, stride) \ - if (addr) { \ - flush_addr = addr; \ - flush_size = fb->height * stride; \ - if (flush_size > l2_cache_size) { \ - flush_addr += flush_size - l2_cache_size; \ - flush_size = l2_cache_size; \ - } \ - sifive_l2_flush64_range(flush_addr, flush_size); \ - } - - FLUSH_FB_PLANE(fb->y_address, fb->y_stride); - FLUSH_FB_PLANE(fb->u_address, fb->u_stride); - FLUSH_FB_PLANE(fb->v_address, fb->v_stride); - -#undef FLUSH_FB_PLANE - } + sifive_l2_flush64_range(fb->y_address, fb->height * fb->y_stride); + if (fb->u_address) + sifive_l2_flush64_range(fb->u_address, fb->height * fb->u_stride); + if (fb->v_address) + sifive_l2_flush64_range(fb->v_address, fb->height * fb->v_stride); plane_state->status.tile_mode = fb->tile_mode; } |