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author | Dave Airlie <airlied@redhat.com> | 2016-11-11 02:31:27 +0300 |
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committer | Dave Airlie <airlied@redhat.com> | 2016-11-11 02:31:27 +0300 |
commit | 628d16555e019c0cc6897b603bbea29c3b6d2c9f (patch) | |
tree | 27159fc9e6c0922802dbe7c7be88fb8b7af115d3 /drivers/gpu/ipu-v3/ipu-cpmem.c | |
parent | 3e91168a6a76f7e21c44f04ebf953589ca59f03c (diff) | |
parent | b5b457b33dcd2a6aa6f70a07f8a9b469727ffeec (diff) | |
download | linux-628d16555e019c0cc6897b603bbea29c3b6d2c9f.tar.xz |
Merge tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm plane update cleanup, YUV formats
- request modeset if plane offsets changed, only the plane base
address can be changed without disabling the plane IDMAC channel.
- cleanup of plane atomic_update
- remove unused ipu_cpmem_set_yuv_planar function
- support YUV 4:4:4, 4:2:2, NV12 and NV16 plane formats
- not only mask interrupts during irq init, also clear them
- remove a legacy check from imx-ldb
- add support to set the CSI downsizing bits
- silence an obnoxious warning during modeset
* tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux:
gpu: ipu-di: silence videomode logspam
gpu: ipu-v3: add ipu_csi_set_downsize
drm/imx: imx-ldb: remove unnecessary double disable check
gpu: ipu-v3: initially clear all interrupts
drm/imx: ipuv3-plane: add support for YUV 4:2:2 and 4:4:4, NV12, and NV16 formats
gpu: ipu-v3: add YUV 4:4:4 support
gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function
drm/imx: ipuv3-plane: let drm_plane_state_to_ubo/vbo handle chroma subsampling other than 4:2:0
drm/imx: ipuv3-plane: merge ipu_plane_atomic_set_base into atomic_update
drm/imx: ipuv3-plane: request modeset if plane offsets changed
Diffstat (limited to 'drivers/gpu/ipu-v3/ipu-cpmem.c')
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-cpmem.c | 43 |
1 files changed, 7 insertions, 36 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c index fcb7dc86167b..4b2b67113d92 100644 --- a/drivers/gpu/ipu-v3/ipu-cpmem.c +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c @@ -417,42 +417,6 @@ void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, } EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); -void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, - u32 pixel_format, int stride, int height) -{ - int fourcc, u_offset, v_offset; - int uv_stride = 0; - - fourcc = v4l2_pix_fmt_to_drm_fourcc(pixel_format); - switch (fourcc) { - case DRM_FORMAT_YUV420: - uv_stride = stride / 2; - u_offset = stride * height; - v_offset = u_offset + (uv_stride * height / 2); - break; - case DRM_FORMAT_YVU420: - uv_stride = stride / 2; - v_offset = stride * height; - u_offset = v_offset + (uv_stride * height / 2); - break; - case DRM_FORMAT_YUV422: - uv_stride = stride / 2; - u_offset = stride * height; - v_offset = u_offset + (uv_stride * height); - break; - case DRM_FORMAT_NV12: - case DRM_FORMAT_NV16: - uv_stride = stride; - u_offset = stride * height; - v_offset = 0; - break; - default: - return; - } - ipu_cpmem_set_yuv_planar_full(ch, uv_stride, u_offset, v_offset); -} -EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar); - static const struct ipu_rgb def_xrgb_32 = { .red = { .offset = 16, .length = 8, }, .green = { .offset = 8, .length = 8, }, @@ -590,6 +554,13 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) /* burst size */ ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); break; + case DRM_FORMAT_YUV444: + case DRM_FORMAT_YVU444: + /* pix format */ + ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0); + /* burst size */ + ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); + break; case DRM_FORMAT_NV12: /* pix format */ ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4); |