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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2019-11-19 17:41:46 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2019-12-16 13:53:05 +0300
commit5908a3bd175d42df5c9946e78cee2d0221787bd4 (patch)
tree18ec0c22f011018e4e3aa0bd0658bda8d18ab89b /drivers/gpu/drm
parent491b14b9ba92e006a8b9d3c973809872b01dd095 (diff)
downloadlinux-5908a3bd175d42df5c9946e78cee2d0221787bd4.tar.xz
DRM: ARC: PGU: replace unsupported by HW RGB888 format by XRGB888
ARC PGU doesn't support RGB888 (24 bit) format but supports XRGB888 (32 bit) format. Fix incorrect format list in a driver. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/arc/arcpgu_crtc.c6
-rw-r--r--drivers/gpu/drm/arc/arcpgu_regs.h2
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c
index 5473b19a52ee..980e00180e6f 100644
--- a/drivers/gpu/drm/arc/arcpgu_crtc.c
+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
@@ -22,7 +22,7 @@
static const u32 arc_pgu_supported_formats[] = {
DRM_FORMAT_RGB565,
- DRM_FORMAT_RGB888,
+ DRM_FORMAT_XRGB8888,
};
static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
@@ -44,9 +44,9 @@ static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
if (format == DRM_FORMAT_RGB565)
- reg_ctrl &= ~ARCPGU_MODE_RGB888_MASK;
+ reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
else
- reg_ctrl |= ARCPGU_MODE_RGB888_MASK;
+ reg_ctrl |= ARCPGU_MODE_XRGB8888;
arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
}
diff --git a/drivers/gpu/drm/arc/arcpgu_regs.h b/drivers/gpu/drm/arc/arcpgu_regs.h
index dab2c380f7f3..b689a382d556 100644
--- a/drivers/gpu/drm/arc/arcpgu_regs.h
+++ b/drivers/gpu/drm/arc/arcpgu_regs.h
@@ -25,7 +25,7 @@
#define ARCPGU_CTRL_VS_POL_OFST 0x3
#define ARCPGU_CTRL_HS_POL_MASK 0x1
#define ARCPGU_CTRL_HS_POL_OFST 0x4
-#define ARCPGU_MODE_RGB888_MASK 0x04
+#define ARCPGU_MODE_XRGB8888 BIT(2)
#define ARCPGU_STAT_BUSY_MASK 0x02
#endif