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authorImre Deak <imre.deak@intel.com>2020-02-26 23:34:54 +0300
committerImre Deak <imre.deak@intel.com>2020-03-02 20:36:21 +0300
commit540a8b6b0eb7492cfa452fe99814c198c2c92e06 (patch)
treed0cf177ad07d646fbc261a566c6f853e084e5234 /drivers/gpu/drm
parentb953eb2153a34a113ec8f4c991390d36e5b00d4b (diff)
downloadlinux-540a8b6b0eb7492cfa452fe99814c198c2c92e06.tar.xz
drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
Instead of reading out the WRPLL/SPLL control values from HW, we can use the DPLL state that was already read out, or swapped-to. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-13-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpll_mgr.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b87b4ff5de52..7e6da58a47c9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
const struct intel_shared_dpll *pll)
{
- i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
- WRPLL_CTL(0) : WRPLL_CTL(1);
int refclk;
int n, p, r;
- u32 wrpll;
+ u32 wrpll = pll->state.hw_state.wrpll;
- wrpll = intel_de_read(dev_priv, reg);
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/*
@@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
{
int link_clock = 0;
- switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
+ switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
case SPLL_FREQ_810MHz:
link_clock = 81000;
break;