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authorThierry Reding <treding@nvidia.com>2015-01-19 18:15:04 +0300
committerThierry Reding <treding@nvidia.com>2015-06-12 17:23:50 +0300
commit4553f733c68b66ef49f838aa24470d58caf76ff5 (patch)
treed6d170f2bdc1d0fa3f6f8f539effadb837423241 /drivers/gpu/drm/tegra/drm.c
parent3c1dae0a07c651526f8e878d223a88f82caa5a50 (diff)
downloadlinux-4553f733c68b66ef49f838aa24470d58caf76ff5.tar.xz
drm/tegra: gem: Take into account IOMMU aperture
The IOMMU may not always be able to address 2 GiB of memory. On Tegra20, the GART supports 32 MiB starting at 0x58000000. Also the aperture on Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as currently assumed. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/drm.c')
-rw-r--r--drivers/gpu/drm/tegra/drm.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 1833abd7d3aa..106208463b37 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -124,14 +124,22 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
return -ENOMEM;
if (iommu_present(&platform_bus_type)) {
+ struct iommu_domain_geometry *geometry;
+ u64 start, end;
+
tegra->domain = iommu_domain_alloc(&platform_bus_type);
if (!tegra->domain) {
err = -ENOMEM;
goto free;
}
- DRM_DEBUG("IOMMU context initialized\n");
- drm_mm_init(&tegra->mm, 0, SZ_2G);
+ geometry = &tegra->domain->geometry;
+ start = geometry->aperture_start;
+ end = geometry->aperture_end;
+
+ DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n",
+ start, end);
+ drm_mm_init(&tegra->mm, start, end - start + 1);
}
mutex_init(&tegra->clients_lock);