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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-11-04 21:26:49 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-05 13:48:23 +0300 |
| commit | c50519e6db4d6425538cdc1a6df5f3cec35997fd (patch) | |
| tree | c986d675731b92c9a9c58f70dc1a30b843620928 /drivers/gpu/drm/sun4i/sun8i_mixer.c | |
| parent | 97eb57feda80b7bf63ae9f74683b38ea21166eb9 (diff) | |
| download | linux-c50519e6db4d6425538cdc1a6df5f3cec35997fd.tar.xz | |
drm/sun4i: Add basic support for DE3
Display Engine 3 is an upgrade of DE2 with new features like support for
10 bit color formats and support for AFBC.
Most of DE2 code works with DE3, except some small details.
Implement basic support for DE3. Support for 10 bit colort formats and
AFBC, among others missing features, will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/260238/
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun8i_mixer.c')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_mixer.c | 39 |
1 files changed, 27 insertions, 12 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 3c2ce2781fc8..ca402cf0f5ba 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -459,18 +459,33 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, base = sun8i_blender_base(mixer); - /* Reset the registers */ - for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) - regmap_write(mixer->engine.regs, i, 0); - - /* Disable unused sub-engines */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0); - regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); + /* Reset registers and disable unused sub-engines */ + if (mixer->cfg->is_de3) { + for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) + regmap_write(mixer->engine.regs, i, 0); + + regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); + } else { + for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) + regmap_write(mixer->engine.regs, i, 0); + + regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0); + regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); + } /* Enable the mixer */ regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, |