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authorDave Airlie <airlied@redhat.com>2013-07-16 04:19:44 +0400
committerDave Airlie <airlied@redhat.com>2013-07-16 04:19:44 +0400
commitd4639ebadb758219ccef97d1f37c0ac44c53de5a (patch)
treeac0337b034e5e6bea056c7e83c173d4926092aab /drivers/gpu/drm/radeon/radeon_ring.c
parentad81f0545ef01ea651886dddac4bef6cec930092 (diff)
parenta01c34f72e7cd2624570818f579b5ab464f93de2 (diff)
downloadlinux-d4639ebadb758219ccef97d1f37c0ac44c53de5a.tar.xz
Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux
More DPM fixes, r6xx DMA fix for bo moving, UVD fixes, one major regression fix on bootup on some machine (ttm backoff missing) * 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux: radeon kms: do not flush uninitialized hotplug work drm/radeon/dpm/sumo: handle boost states properly when forcing a perf level drm/radeon: align VM PTBs (Page Table Blocks) to 32K drm/radeon: allow selection of alignment in the sub-allocator drm/radeon: never unpin UVD bo v3 drm/radeon: fix UVD fence emit drm/radeon: add fault decode function for CIK drm/radeon: add fault decode function for SI (v2) drm/radeon: add fault decode function for cayman/TN (v2) drm/radeon: use radeon device for request firmware drm/radeon: add missing ttm_eu_backoff_reservation to radeon_bo_list_validate drm/radeon: use CP DMA on r6xx for bo moves drm/radeon: implement bo copy callback using CP DMA (v2) drm/radeon: Disable dma rings for bo moves on r6xx drm/radeon/dpm: disable gfx PG on PALM drm/radeon/hdmi: make sure we have an afmt block assigned
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_ring.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 5f1c51a776ed..fb5ea6208970 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -224,6 +224,7 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
}
r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
RADEON_IB_POOL_SIZE*64*1024,
+ RADEON_GPU_PAGE_SIZE,
RADEON_GEM_DOMAIN_GTT);
if (r) {
return r;