summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/radeon/radeon.h
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2014-08-28 05:39:11 +0400
committerDave Airlie <airlied@redhat.com>2014-08-28 05:39:11 +0400
commit6adae108b2fb0c7b945e297e4a0f0b7d66599656 (patch)
treef27fd0ebf1c21fe4690da58d0675ca6117419cf6 /drivers/gpu/drm/radeon/radeon.h
parentfb1aacae408a48968840f8743a73edaad94a2f94 (diff)
parent3c0363891c0fa5d17b683b758bff0d81fa6a9775 (diff)
downloadlinux-6adae108b2fb0c7b945e297e4a0f0b7d66599656.tar.xz
Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux into drm-next
More radeon changes for drm-next. Highlights: - UVD support for older asics - Reset rework in preparation for Maarten's fence patches I have a few more patches which depend on Christian's ttm changes, I'll send them out separately once you've merged the ttm changes. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: drop doing resets in a work item drm/radeon: drop RADEON_FENCE_SIGNALED_SEQ v2 drm/radeon: add timeout argument to radeon_fence_wait_seq v2 drm/radeon: handle lockup in delayed work, v5 drm/radeon: take exclusive_lock in read mode during ring tests, v5 drm/radeon: force fence completion only on problematic rings (v2) drm/radeon: wake up all fences on manual reset drm/radeon: add UVD fw names for older asic drm/radeon: enable RB_ARB before resetting the VCPU drm/radeon: 760G/780V/880V don't have UVD drm/radeon: implement UVD hw workarounds for R6xx v3 drm/radeon: add UVD support for older asics v4 drm/radeon: add set_uvd_clocks callback for r6xx v4 drm/radeon: properly init UVD MC bits on R600 drm/radeon: force UVD buffers into VRAM on RS[78]80 v2 drm/radeon: move the IB test after the AGP fallback
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h10
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index bb01dab513dd..a5ac95bf05ea 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -120,9 +120,6 @@ extern int radeon_bapm;
#define RADEONFB_CONN_LIMIT 4
#define RADEON_BIOS_NUM_SCRATCH 8
-/* fence seq are set to this number when signaled */
-#define RADEON_FENCE_SIGNALED_SEQ 0LL
-
/* internal ring indices */
/* r1xx+ has gfx CP ring */
#define RADEON_RING_TYPE_GFX_INDEX 0
@@ -350,6 +347,7 @@ extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
* Fences.
*/
struct radeon_fence_driver {
+ struct radeon_device *rdev;
uint32_t scratch_reg;
uint64_t gpu_addr;
volatile uint32_t *cpu_addr;
@@ -357,6 +355,7 @@ struct radeon_fence_driver {
uint64_t sync_seq[RADEON_NUM_RINGS];
atomic64_t last_seq;
bool initialized;
+ struct delayed_work lockup_work;
};
struct radeon_fence {
@@ -371,7 +370,7 @@ struct radeon_fence {
int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
int radeon_fence_driver_init(struct radeon_device *rdev);
void radeon_fence_driver_fini(struct radeon_device *rdev);
-void radeon_fence_driver_force_completion(struct radeon_device *rdev);
+void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
void radeon_fence_process(struct radeon_device *rdev, int ring);
bool radeon_fence_signaled(struct radeon_fence *fence);
@@ -2326,7 +2325,7 @@ struct radeon_device {
bool need_dma32;
bool accel_working;
bool fastfb_working; /* IGP feature*/
- bool needs_reset;
+ bool needs_reset, in_reset;
struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
const struct firmware *me_fw; /* all family ME firmware */
const struct firmware *pfp_fw; /* r6/700 PFP firmware */
@@ -2347,7 +2346,6 @@ struct radeon_device {
struct radeon_mec mec;
struct work_struct hotplug_work;
struct work_struct audio_work;
- struct work_struct reset_work;
int num_crtc; /* number of crtcs */
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
bool has_uvd;