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author | Alex Deucher <alexander.deucher@amd.com> | 2014-09-15 07:45:30 +0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2014-11-12 19:56:35 +0300 |
commit | 1955f107a7bf5c9f718bf5025a24f5ff1607d7b2 (patch) | |
tree | 25c53127ceb9140513ce3cb8b087860afc8225b6 /drivers/gpu/drm/radeon/ppsmc.h | |
parent | 2271e2e2a2525f826549f1aa19db36e0b80082fe (diff) | |
download | linux-1955f107a7bf5c9f718bf5025a24f5ff1607d7b2.tar.xz |
drm/radeon: rework CI dpm thermal setup
In preparation for fan control.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ppsmc.h')
-rw-r--r-- | drivers/gpu/drm/radeon/ppsmc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h index 5670b8291285..11c0e4d5c0bf 100644 --- a/drivers/gpu/drm/radeon/ppsmc.h +++ b/drivers/gpu/drm/radeon/ppsmc.h @@ -106,6 +106,7 @@ typedef uint8_t PPSMC_Result; #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) @@ -157,10 +158,11 @@ typedef uint8_t PPSMC_Result; #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) -#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) |