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authorDave Airlie <airlied@redhat.com>2014-03-18 13:12:31 +0400
committerDave Airlie <airlied@redhat.com>2014-03-18 13:12:31 +0400
commitbcc298bc924e0a990f853ba3e19f8b5a833cba7e (patch)
tree1c87c8f73dc41fd11ee3dacb1b91a7cc8b4798bb /drivers/gpu/drm/radeon/cik_sdma.c
parent978c6050165bba52eab7ef3581d447eb215def77 (diff)
parentdcb99fd9b08cfe1afe426af4d8d3cbc429190f15 (diff)
downloadlinux-bcc298bc924e0a990f853ba3e19f8b5a833cba7e.tar.xz
Merge tag 'v3.14-rc7' into drm-next
Linux 3.14-rc7 Backmerge to help out Intel guys.
Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 00150ac49cd2..89b4afa5041c 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -264,6 +264,8 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
}
+ rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
+ rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
}
/**
@@ -291,6 +293,11 @@ void cik_sdma_enable(struct radeon_device *rdev, bool enable)
u32 me_cntl, reg_offset;
int i;
+ if (enable == false) {
+ cik_sdma_gfx_stop(rdev);
+ cik_sdma_rlc_stop(rdev);
+ }
+
for (i = 0; i < 2; i++) {
if (i == 0)
reg_offset = SDMA0_REGISTER_OFFSET;
@@ -418,10 +425,6 @@ static int cik_sdma_load_microcode(struct radeon_device *rdev)
if (!rdev->sdma_fw)
return -EINVAL;
- /* stop the gfx rings and rlc compute queues */
- cik_sdma_gfx_stop(rdev);
- cik_sdma_rlc_stop(rdev);
-
/* halt the MEs */
cik_sdma_enable(rdev, false);
@@ -490,9 +493,6 @@ int cik_sdma_resume(struct radeon_device *rdev)
*/
void cik_sdma_fini(struct radeon_device *rdev)
{
- /* stop the gfx rings and rlc compute queues */
- cik_sdma_gfx_stop(rdev);
- cik_sdma_rlc_stop(rdev);
/* halt the MEs */
cik_sdma_enable(rdev, false);
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);