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authorBen Skeggs <bskeggs@redhat.com>2014-08-09 22:10:25 +0400
committerBen Skeggs <bskeggs@redhat.com>2014-08-09 23:28:04 +0400
commitbbf8906b2cad17cf9530b06db7509d0e39b02d16 (patch)
tree8b0ac662278cd6ea528c619d4ebd932f67a29fe3 /drivers/gpu/drm/nouveau/nouveau_drm.c
parenta532da976f17234375d3b34633ff5d48f71f62bc (diff)
downloadlinux-bbf8906b2cad17cf9530b06db7509d0e39b02d16.tar.xz
drm/nouveau/fifo: audit and version fifo channel classes
The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drm.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 44f168c356ca..f11b65195337 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -156,24 +156,24 @@ nouveau_accel_init(struct nouveau_drm *drm)
for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) {
switch (sclass[i]) {
- case NV03_CHANNEL_DMA_CLASS:
+ case NV03_CHANNEL_DMA:
ret = nv04_fence_create(drm);
break;
- case NV10_CHANNEL_DMA_CLASS:
+ case NV10_CHANNEL_DMA:
ret = nv10_fence_create(drm);
break;
- case NV17_CHANNEL_DMA_CLASS:
- case NV40_CHANNEL_DMA_CLASS:
+ case NV17_CHANNEL_DMA:
+ case NV40_CHANNEL_DMA:
ret = nv17_fence_create(drm);
break;
- case NV50_CHANNEL_IND_CLASS:
+ case NV50_CHANNEL_GPFIFO:
ret = nv50_fence_create(drm);
break;
- case NV84_CHANNEL_IND_CLASS:
+ case G82_CHANNEL_GPFIFO:
ret = nv84_fence_create(drm);
break;
- case NVC0_CHANNEL_IND_CLASS:
- case NVE0_CHANNEL_IND_CLASS:
+ case FERMI_CHANNEL_GPFIFO:
+ case KEPLER_CHANNEL_GPFIFO_A:
ret = nvc0_fence_create(drm);
break;
default:
@@ -189,13 +189,13 @@ nouveau_accel_init(struct nouveau_drm *drm)
if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
- NVE0_CHANNEL_IND_ENGINE_CE0 |
- NVE0_CHANNEL_IND_ENGINE_CE1, 0,
- &drm->cechan);
+ KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0|
+ KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1,
+ 0, &drm->cechan);
if (ret)
NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
- arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
+ arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR;
arg1 = 1;
} else
if (device->info.chipset >= 0xa3 &&