diff options
| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-06-07 17:19:03 +0300 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-07-15 15:51:25 +0300 |
| commit | 738fa1b3123f9a3b4374b4156ad54a2b64273f51 (patch) | |
| tree | 7e5755e8b28f397ddb87f47258f2aa87ee1e28d9 /drivers/gpu/drm/i915/intel_lrc.c | |
| parent | 9146f308d5916e20c53afe3ee0bd4dbd562a0ef9 (diff) | |
| download | linux-738fa1b3123f9a3b4374b4156ad54a2b64273f51.tar.xz | |
drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
v2: Fix KBL_REVID_E0 (Matthew)
References: HSD#2132677
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-12-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit fe90581987cd5fadd2942f59f8511bcb39fdec34)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 42eac37de047..cf18eace6690 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1103,15 +1103,17 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, uint32_t *const batch, uint32_t index) { + struct drm_i915_private *dev_priv = engine->dev->dev_private; uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); /* - * WaDisableLSQCROPERFforOCL:skl + * WaDisableLSQCROPERFforOCL:skl,kbl * This WA is implemented in skl_init_clock_gating() but since * this batch updates GEN8_L3SQCREG4 with default value we need to * set this bit here to retain the WA during flush. */ - if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0)) + if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) || + IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |