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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-07-06 14:44:11 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-07-13 12:10:05 +0300
commit5e6ccc0b3d16725028caccceb2460fc3473d7d55 (patch)
tree087d303ac68cf97d49eb590c9cee1d84e71961fd /drivers/gpu/drm/i915/intel_hdmi.c
parent2be7d540fde3f82e404cbddeeb2fdf05cf33af3c (diff)
downloadlinux-5e6ccc0b3d16725028caccceb2460fc3473d7d55.tar.xz
drm/i915: Adjust BXT HDMI port clock limits
Since commit e62925567c7926e78bc8ca976cde5c28ea265a49 Author: Vandana Kannan <vandana.kannan@intel.com> Date: Wed Jul 1 17:02:57 2015 +0530 drm/i915/bxt: BUNs related to port PLL BXT DPLL can now generate frequencies in the 216-223 MHz range. Adjust the HDMI port clock checks to account for the reduced range of invalid frequencies. Cc: Vandana Kannan <vandana.kannan@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c7e912bafb87..70bad5bf1d48 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1174,9 +1174,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
return MODE_CLOCK_HIGH;
- /* CHV/BXT DPLL can't generate 216-240 MHz */
- if ((IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) &&
- clock > 216000 && clock < 240000)
+ /* BXT DPLL can't generate 223-240 MHz */
+ if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
+ return MODE_CLOCK_RANGE;
+
+ /* CHV DPLL can't generate 216-240 MHz */
+ if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
return MODE_CLOCK_RANGE;
return MODE_OK;