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authorAdam Jackson <ajax@redhat.com>2011-07-26 23:39:45 +0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-01-17 19:46:56 +0400
commit092945e11c5b84f66dd08f0b87fb729715d377bc (patch)
tree82291ff665b5b51e7098c0348a91902c332fc27e /drivers/gpu/drm/i915/intel_dp.c
parent6919132e7a307b1f181d7655b3ef64cc7581a5ef (diff)
downloadlinux-092945e11c5b84f66dd08f0b87fb729715d377bc.tar.xz
drm/i915/dp: Use auxch precharge value of 5 everywhere
The default in the Sandybridge docs is 5, as on Ironlake, and I have no reason to believe 3 would work any better. Signed-off-by: Adam Jackson <ajax@redhat.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index add871911a63..2f4766385797 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -362,7 +362,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
int recv_bytes;
uint32_t status;
uint32_t aux_clock_divider;
- int try, precharge;
+ int try, precharge = 5;
intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk,
@@ -382,11 +382,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = intel_hrawclk(dev) / 2;
- if (IS_GEN6(dev))
- precharge = 3;
- else
- precharge = 5;
-
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ(ch_ctl);