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authorChris Wilson <chris@chris-wilson.co.uk>2011-03-02 02:20:20 +0300
committerChris Wilson <chris@chris-wilson.co.uk>2011-03-02 02:20:20 +0300
commit8d3c3ddfa85837e24fad6fa39318617cbb59e843 (patch)
treef699dcaac2a11f0c9506ad111ae39fd5e3617c2d /drivers/gpu/drm/i915/i915_dma.c
parente8b2c3c47a53348aebbbeb5322e32937df958793 (diff)
parent6927faf30920b8c03dfa007e732642a1f1f20089 (diff)
downloadlinux-8d3c3ddfa85837e24fad6fa39318617cbb59e843.tar.xz
Merge branch 'drm-intel-fixes' into drm-intel-next
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 51150692af2d..8924b4bc7369 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1900,6 +1900,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (IS_GEN2(dev))
dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
+ /* 965GM sometimes incorrectly writes to hardware status page (HWS)
+ * using 32bit addressing, overwriting memory if HWS is located
+ * above 4GB.
+ *
+ * The documentation also mentions an issue with undefined
+ * behaviour if any general state is accessed within a page above 4GB,
+ * which also needs to be handled carefully.
+ */
+ if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+ dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
+
mmio_bar = IS_GEN2(dev) ? 1 : 0;
dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
if (!dev_priv->regs) {