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| author | Changbin Du <changbin.du@intel.com> | 2018-01-30 14:19:40 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-03-06 08:19:13 +0300 |
| commit | ede9d0cfcb789b6fd86ecb71b4721a19c53956e6 (patch) | |
| tree | fa844b6b6c549c0d7b342cc7fed4e3777f520a80 /drivers/gpu/drm/i915/gvt/scheduler.c | |
| parent | 1f267a572b573b0b155022750cba93001f4367a8 (diff) | |
| download | linux-ede9d0cfcb789b6fd86ecb71b4721a19c53956e6.tar.xz | |
drm/i915/gvt: Rework shadow graphic memory management code
This is a big one and the GVT shadow graphic memory management code is
heavily refined. The new code is more straightforward with less code.
The struct intel_vgpu_mm is restructured to be clearly defined, use
accurate names and some of the original fields are removed which are
really redundant.
Now we only manage ppgtt mm object with mm->ppgtt_mm.lru_list. No need
to mix ppgtt and ggtt together, since one vGPU only has one ggtt object.
v4: Don't invoke ppgtt_free_all_shadow_page before intel_vgpu_destroy_all_ppgtt_mm.
v3: Add GVT_RING_CTX_NR_PDPS to avoid confusing about the PDPs.
v2: Split some changes into small standalone patches.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/scheduler.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/scheduler.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 92df1b44fe1d..5668c3d0f542 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -113,7 +113,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) #undef COPY_REG set_context_pdp_root_pointer(shadow_ring_context, - workload->shadow_mm->shadow_page_table); + (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa + @@ -1181,27 +1181,30 @@ static int prepare_mm(struct intel_vgpu_workload *workload) struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc; struct intel_vgpu_mm *mm; struct intel_vgpu *vgpu = workload->vgpu; - int page_table_level; - u32 pdp[8]; + intel_gvt_gtt_type_t root_entry_type; + u64 pdps[GVT_RING_CTX_NR_PDPS]; - if (desc->addressing_mode == 1) { /* legacy 32-bit */ - page_table_level = 3; - } else if (desc->addressing_mode == 3) { /* legacy 64 bit */ - page_table_level = 4; - } else { + switch (desc->addressing_mode) { + case 1: /* legacy 32-bit */ + root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; + break; + case 3: /* legacy 64-bit */ + root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; + break; + default: gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n"); return -EINVAL; } - read_guest_pdps(workload->vgpu, workload->ring_context_gpa, pdp); + read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps); - mm = intel_vgpu_find_ppgtt_mm(workload->vgpu, page_table_level, pdp); + mm = intel_vgpu_find_ppgtt_mm(workload->vgpu, pdps); if (mm) { intel_gvt_mm_reference(mm); } else { - mm = intel_vgpu_create_mm(workload->vgpu, INTEL_GVT_MM_PPGTT, - pdp, page_table_level, 0); + mm = intel_vgpu_create_ppgtt_mm(workload->vgpu, root_entry_type, + pdps); if (IS_ERR(mm)) { gvt_vgpu_err("fail to create mm object.\n"); return PTR_ERR(mm); |