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| author | Changbin Du <changbin.du@intel.com> | 2018-05-15 05:35:33 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-07-09 05:22:30 +0300 |
| commit | b294657d1bab3371bf02c31a243232bfa9f4629f (patch) | |
| tree | a46d75f1597acd5499d81ab343ab511d1908ee3a /drivers/gpu/drm/i915/gvt/gtt.h | |
| parent | 57c8a484a9cbf1315b5299702d12aef04867eeee (diff) | |
| download | linux-b294657d1bab3371bf02c31a243232bfa9f4629f.tar.xz | |
drm/i915/gvt: Add new 64K entry type
Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very
different from 2M/1G entry. 64K entry is controlled by IPS bit in upper
PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE
level. Which means, 64K entries can also processed by get_pse_type().
v2: Make it bisectable.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/gtt.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index 3792f2b7f4ff..60630816df5c 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -95,6 +95,7 @@ typedef enum { GTT_TYPE_GGTT_PTE, GTT_TYPE_PPGTT_PTE_4K_ENTRY, + GTT_TYPE_PPGTT_PTE_64K_ENTRY, GTT_TYPE_PPGTT_PTE_2M_ENTRY, GTT_TYPE_PPGTT_PTE_1G_ENTRY, |